C8051F54X_14 Datasheet, PDF (55/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 6.9. ADC0 Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified.
Parameter
DC Accuracy
Conditions
Min Typ
Max
Units
Resolution
12
bits
Integral Nonlinearity
—
±0.5
±3
LSB
Differential Nonlinearity
Offset Error¹
Full Scale Error
Guaranteed Monotonic
—
±0.5
±1
LSB
–10
3.0
10
LSB
–20
5.7
20
LSB
Offset Temperature Coefficient
—
7.7
—
ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
63
65
—
dB
Total Harmonic Distortion
Up to the 5th harmonic;
—
80
—
dB
Spurious-Free Dynamic Range
—
-82
—
dB
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks²
Track/Hold Acquisition Time³
VDDA > 2.0 V
VDDA < 2.0 V
Throughput Rate⁴
VDDA > 2.0 V
Analog Inputs
—
—
13
—
1.5
—
3.5
—
—
—
3.6
MHz
—
clocks
—
µs
—
200
ksps
ADC Input Voltage Range⁵
gain = 1.0 (default)
gain = n
Absolute Pin Voltage with respect
to GND
Sampling Capacitance
0
—
VREF
V
0
VREF / n
0
—
V_IO
V
—
31
—
pF
Input Multiplexer Impedance
—
3
—
k
Power Specifications
Power Supply Current 
(VDDA supplied to ADC0)
Burst Mode (Idle)
Operating Mode, 200 ksps
—
1100 1500
µA
—
1100 1500
µA
Power-On Time
5
—
—
µs
Power Supply Rejection
—
–60
—
mV/V
Notes:
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed through
calibration.
2. An additional 2 FCLK cycles are required to start and complete a conversion
3. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section “5.2.1. Settling Time Requirements” on page 34.
4. An increase in tracking time will decrease the ADC throughput.
5. See Section “5.3. Selectable Gain” on page 35 for more information about the setting the gain.
Rev. 1.1
55