C8051F54X_14 Datasheet, PDF (192/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 20.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 20.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time
Minimum SDA Hold Time
0
T_low – 4 system clocks
3 system clocks
or
1 system clock + s/w delay^*
1
11 system clocks
12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “20.3.4. SCL Low Timeout” on page 189). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 20.4).
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Rev. 1.1