C8051F54X_14 Datasheet, PDF (196/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Bit
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Table 20.3. Sources for Hardware Changes to SMB0CN
Set by Hardware When:
Cleared by Hardware When:
 A START is generated.
 A STOP is generated.
 Arbitration is lost.
 START is generated.
 SMB0DAT is written before the start of an
SMBus frame.
 A START is detected.
 Arbitration is lost.
 SMB0DAT is not written before the
start of an SMBus frame.
 A START followed by an address byte is
received.
 Must be cleared by software.
 A STOP is detected while addressed as a
slave.
 Arbitration is lost due to a detected STOP.
 A pending STOP is generated.
 A byte has been received and an ACK
response value is needed.
 After each ACK cycle.
 A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
 SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
 SDA is sensed low while transmitting a 1
(excluding ACK bits).
 Each time SI is cleared.
 The incoming ACK value is low 
(ACKNOWLEDGE).
 The incoming ACK value is high
(NOT ACKNOWLEDGE).
 A START has been generated.
 Lost arbitration.
 A byte has been transmitted and an
ACK/NACK received.
 A byte has been received.
 A START or repeated START followed by a
slave address + R/W has been received.
 A STOP has been received.
 Must be cleared by software.
196
Rev. 1.1