C8051F54X_14 Datasheet, PDF (162/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.13. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF1; SFR Page = 0x0F
Bit
Name
Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P0MDOUT register.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 18.14. P0MDOUT: Port 0 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA4; SFR Page = 0x0F
Bit
Name
Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
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Rev. 1.1