C8051F54X_14 Datasheet, PDF (25/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

4.2. QFN-32 Package Specifications
C8051F54x
Figure 4.3. QFN-32 Package Drawing
Table 4.3. QFN-32 Package Dimensions
Dimension Min
Typ
Max
Dimension Min
Typ
Max
A
0.80
0.9
1.00
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
5.00 BSC.
D2
3.20
3.30
3.40
e
0.50 BSC.
E
5.00 BSC.
E2
3.20
3.30
3.40
L
0.30
0.40
0.50
L1
0.00
—
0.15
aaa
—
—
0.15
bbb
—
—
0.15
ddd
—
—
0.05
eee
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
25