C8051F54X_14 Datasheet, PDF (101/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 12.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
ACC
0xE0
Accumulator
ADC0CF
0xBC
ADC0 Configuration
ADC0CN
0xE8
ADC0 Control
ADC0GTH
0xC4
ADC0 Greater-Than Compare High
ADC0GTL
0xC3
ADC0 Greater-Than Compare Low
ADC0H
0xBE
ADC0 High
ADC0L
0xBD
ADC0 Low
ADC0LTH
ADC0LTL
ADC0MX
ADC0TK
B
CCH0CN
CKCON
0xC6
0xC5
0xBB
0xBA
0xF0
0xE3
0x8E
ADC0 Less-Than Compare Word High
ADC0 Less-Than Compare Word Low
ADC0 Mux Configuration
ADC0 Tracking Mode Select
B Register
Cache Control
Clock Control
CLKMUL
CLKSEL
CPT0CN
CPT0MD
CPT0MX
CPT1CN
CPT1MD
CPT1MX
DPH
DPL
EIE1
EIE2
EIP1
EIP2
EMI0CN
FLKEY
FLSCL
IE
IP
IT01CF
LIN0ADR
0x97
0x8F
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0x83
0x82
0xE6
0xE7
0xF6
0xF7
0xAA
0xB7
0xB6
0xA8
0xB8
0xE4
0xD3
Clock Multiplier
Clock Select
Comparator0 Control
Comparator0 Mode Selection
Comparator0 MUX Selection
Comparator1 Control
Comparator1 Mode Selection
Comparator1 MUX Selection
Data Pointer High
Data Pointer Low
Extended Interrupt Enable 1
Extended Interrupt Enable 2
Extended Interrupt Priority 1
Extended Interrupt Priority 2
External Memory Interface Control
Flash Lock and Key
Flash Scale
Interrupt Enable
Interrupt Priority
INT0/INT1 Configuration
LIN0 Address
Page
82
40
42
44
44
41
41
45
45
59
43
82
125
228
141
136
65
66
70
65
66
70
81
81
111
111
112
113
88
123
124
109
110
116
177
Rev. 1.1
101