C8051F54X_14 Datasheet, PDF (62/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 7.1. REF0CN: Reference Control
Bit
7
Name
Type
R
Reset
0
6
5
4
3
2
1
0
ZTCEN REFLV REFSL TEMPE BIASE REFBE
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
SFR Address = 0xD1; SFR Page = 0x00
Bit Name
Function
7:6 Unused Read = 00b; Write = don’t care.
5 ZTCEN Zero Temperature Coefficient Bias Enable Bit.
This bit must be set to 1b before entering oscillator suspend mode.
0: ZeroTC Bias Generator automatically enabled when required.
1: ZeroTC Bias Generator forced on.
4 REFLV Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.20 V.
3 REFSL Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: V_REF pin used as voltage reference.
1: V_DD used as voltage reference.
2 TEMPE Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
1 BIASE Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0 REFBE On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the V_REF pin.
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Rev. 1.1