C8051F54X_14 Datasheet, PDF (100/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x0 and 0xF
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
F8 0 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCACPL4 PCACPH4 VDM0CN
F
SN0
SN1
SN2
SN3
F0 0 B
P0MAT P0MASK P1MAT P1MASK
EIP1
EIP2
F (All Pages) P0MDIN P1MDIN P2MDIN P3MDIN
EIP1
EIP2
E8 0 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPL3 RSTSRC
F
E0 0 ACC
EIE1
EIE2
F (All Pages) XBR0
XBR1 CCH0CN IT01CF
(All Pages) (All Pages)
D8 0 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5
F
PCA0PWM
D0 0 PSW REF0CN LIN0DATA LIN0ADDR
F (All Pages)
P0SKIP P1SKIP P2SKIP P3SKIP
C8 0 TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L TMR2H PCA0CPL5 PCA0CPH5
F
LIN0CF
C0 0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
F
XBR2
B8 0 IP
ADC0TK ADC0MX ADC0CF ADC0L ADC0H
F (All Pages)
B0 0 P3
P2MAT P2MASK
FLSCL FLKEY
F (All Pages)
(All Pages) (All Pages)
A8 0 IE
SMOD0 EMI0CN
P3MAT P3MASK
F (All Pages)
SBCON0 SBRLL0 SBRLH0 P3MDOUT
A0 0 P2 SPI0CFG SPI0CKR SPI0DAT
SFRPAGE
F (All Pages) OSCICN OSCICRS
P0MDOUT P1MDOUT P2MDOUT (All Pages)
98 0 SCON0 SBUF0 CPT0CN CPT0MD CPT0MX CPT1CN CPT1MD CPT1MX
F
OSCIFIN OSCXCN
90 0 P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H
F (All Pages)
CLKMUL
88 0 TCON TMOD
TL0
TL1
TH0
TH1
CKCON PSCTL
F (All Pages) (All Pages) (All Pages) (All Pages) (All Pages) (All Pages) (All Pages) CLKSEL
80 0 P0
SP
DPL
DPH
SFRNEXT SFRLAST PCON
F (All Pages) (All Pages) (All Pages) (All Pages) SFR0CN (All Pages) (All Pages) (All Pages)
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
(bit addressable)
100
Rev. 1.1