C8051F54X_14 Datasheet, PDF (18/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F54x
Name
Pin
Pin
‘F540/1/4/5 ‘F542/3/6/7
Type
Description
VDD
GND
VDDA
(32-pin)
4
6
5
GNDA
7
VREGIN
3
VIO
2
RST/
10
C2CK
P2.1/
—
(24-pin)
3
Digital Supply Voltage. Must be connected.
4
Digital Ground. Must be connected.
—
Analog Supply Voltage. Must be connected. Connected
internally to VDD on the 24-pin packages.
5
Analog Ground. Must be connected.
2
Voltage Regulator Input
1
Port I/O Supply Voltage. Must be connected.
8
D I/O Device Reset. Open-drain output of internal POR or
V_DD Monitor.
D I/O ^{Clock signal for the C2 Debug Interface.}
7
D I/O or A In Port 2.1. See SFR Definition 18.20 for a description.
C2D
P3.0/
9
D I/O Bi-directional data signal for the C2 Debug Interface.
— D I/O or A In Port 3.0. See SFR Definition 18.24 for a description.
C2D
P0.0
8
P0.1
1
P0.2
32
P0.3
31
P0.4
30
P0.5
29
P0.6
28
P0.7
27
P1.0
26
P1.1
25
P1.2
24
D I/O Bi-directional data signal for the C2 Debug Interface.
6
D I/O or A In Port 0.0. See SFR Definition 18.12 for a description.
24 D I/O or A In Port 0.1
23 D I/O or A In Port 0.2
22 D I/O or A In Port 0.3
21 D I/O or A In Port 0.4
20 D I/O or A In Port 0.5
19 D I/O or A In Port 0.6
18 D I/O or A In Port 0.7
17 D I/O or A In Port 1.0. See SFR Definition 18.16 for a description.
16 D I/O or A In Port 1.1.
15 D I/O or A In Port 1.2.
18
Rev. 1.1