C8051F54X_14 Datasheet, PDF (211/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 21.2. SMOD0: Serial Port 0 Control
Bit
Name
Type
Reset
7
MCE0
R/W
0
6
5
S0PT[1:0]
R/W
R
0
0
4
3
2
1
0
PE0
S0DL[1:0]
XBE0
SBL0
R/W
R/W
R/W
R/W
R/W
0
1
1
0
0
SFR Address = 0xA9; SFR Page = 0x00
Bit Name
Function
7 MCE0 Multiprocessor Communication Enable.
0: RI0 will be activated if stop bit(s) are 1.
1: RI0 will be activated if stop bit(s) and extra bit are 1. Extra bit must be enabled using
XBE0.
6:5 S0PT[1:0] Parity Type Select Bits.
00: Odd Parity
01: Even Parity
10: Mark Parity
11: Space Parity.
4
PE0 Parity Enable.
This bit enables hardware parity generation and checking. The parity type is selected
by bits S0PT[1:0] when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
3:2 S0DL[1:0] Data Length.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
1 XBE0 Extra Bit Enable.
When enabled, the value of TBX0 will be appended to the data field
0: Extra Bit is disabled.
1: Extra Bit is enabled.
0 SBL0 Stop Bit Length.
0: Short—stop bit is active for one bit time
1: Long—stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
Rev. 1.1
211