C8051F54X_14 Datasheet, PDF (132/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 16.1. VDM0CN: V_DD Monitor Control
Bit
7
6
5
4
3
2
1
0
Name ^{VDMEN VDDSTAT VDMLVL}
Type ^R/W
R
R/W
R
R
R
R
R
Reset ^Varies
Varies
0
0
0
0
0
0
SFR Address = 0xFF; SFR Page = 0x00
Bit
Name
Function
7
VDMEN V_DD Monitor Enable.
This bit turns the V_DD monitor circuit on/off. The V_DD Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 16.2). Selecting the V_DD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V_DD Monitor and selecting it as a
reset source. See Table 6.4 for the minimum V_DD Monitor turn-on time.
0: V_DD Monitor Disabled.
1: V_DD Monitor Enabled.
6 VDDSTAT V_DD Status.
This bit indicates the current power supply status (V_DD Monitor output).
0: V_DD is at or below the V_DD monitor threshold.
1: V_DD is above the V_DD monitor threshold.
5
VDMLVL V_DD Monitor Level Select.
0: V_DD Monitor Threshold is set to VRST-LOW
1: V_DD Monitor Threshold is set to VRST-HIGH. This setting is required for any sys-
tem includes code that writes to and/or erases Flash.
4:0 Unused Read = 00000b; Write = Don’t care.
16.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 6.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
16.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the time specified in Table 6.4, “Reset Electrical Characteristics,”
on page 52, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RST-
SRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the
MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaf-
fected by this reset.
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Rev. 1.1