C8051F54X_14 Datasheet, PDF (202/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Values Read
Table 20.4. SMBus Status Decoding
Current SMbus State
Typical Response Options
Values to
Write
1110 0 0 X A master START was gener- Load slave address + R/W into 0 0 X 1100
ated.
SMB0DAT.
1100 0 0 0 A master data or address byte Set STA to restart transfer.
was transmitted; NACK
received.
Abort transfer.
1 0 X 1110
01X —
0 0 1 A master data or address byte Load next data byte into
was transmitted; ACK
SMB0DAT.
received.
End transfer with STOP.
0 0 X 1100
01X —
End transfer with STOP and start 1 1 X —
another transfer.
Send repeated START.
1 0 X 1110
Switch to Master Receiver Mode 0 0 X 1000
(clear SI without writing new data
to SMB0DAT).
1000 1 0 X A master data byte was
received; ACK requested.
Acknowledge received byte;
Read SMB0DAT.
0 0 1 1000
Send NACK to indicate last byte, 0 1 0 —
and send STOP.
Send NACK to indicate last byte, 1 1 0 1110
and send STOP followed by
START.
Send ACK followed by repeated 1 0 1 1110
START.
Send NACK to indicate last byte, 1 0 0 1110
and send repeated START.
Send ACK and switch to Master 0 0 1 1100
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas- 0 0 0 1100
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
202
Rev. 1.1