C8051F54X_14 Datasheet, PDF (254/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
xx
000x
PCA Interrupt
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
543210
Port I/O
Crossbar ^CEXn
0
1
0
1
PCA0CPLn PCA0CPHn
Capture
PCA
Timebase
PCA0L
PCA0H
Figure 24.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
24.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
254
Rev. 1.1