C8051F54X_14 Datasheet, PDF (48/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
6.2. Electrical Characteristics
Table 6.2. Global Electrical Characteristics
–40 to +125 °C, 24 MHz system clock unless otherwise specified.
Parameter
Conditions
Min Typ Max
Supply Input Voltage (V_REGIN)
1.8 — 5.25
Digital Supply Voltage (V_DD) System Clock < 25 MHz
V_RST1 ^{— 2.75}
System Clock > 25 MHz
2
— 2.75
Analog Supply Voltage (VDDA) System Clock < 25 MHz
V_RST1 ^{— 2.75}
(Must be connected to V_DD) System Clock > 25 MHz
2
2.75
Port I/O Supply Voltage (V_IO) Normal Operation
1.8^{2 — 5.25}
Digital Supply RAM Data
Retention Voltage
— 1.5 —
SYSCLK (System Clock)³
0
— 50
T_SYSH (SYSCLK High Time)
9
——
T_SYSL (SYSCLK Low Time)
9
——
Specified Operating
Temperature Range
–40 — +125
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
I_DD4
V_DD = 2.1 V, F = 200 kHz
— 85 —
V_DD = 2.1 V, F = 1.5 MHz
— 600 —
V_DD = 2.1 V, F = 25 MHz
— 9.2 11
V_DD = 2.1 V, F = 50 MHz
— 17 21
I_DD4
V_DD = 2.6 V, F = 200 kHz
— 120 —
V_DD = 2.6 V, F = 1.5 MHz
— 920 —
V_DD = 2.6 V, F = 25 MHz
— 13 21
V_DD = 2.6 V, F = 50 MHz
— 22 33
I_DD Supply Sensitivity⁴
F = 25 MHz
F = 1 MHz
— 68 —
— 77 —
I_DD Frequency Sensitivity ^{4,5 V}DD ^{= 2.1 V, F < 12.5 MHz, T = 25 °C — 0.43 —}
V_DD = 2.1 V, F > 12.5 MHz, T = 25 °C — 0.33 —
V_DD = 2.6 V, F < 12.5 MHz, T = 25 °C — 0.60 —
V_DD = 2.6 V, F > 12.5 MHz, T = 25 °C — 0.42 —
Units
V
V
V
V
V
MHz
ns
ns
°C
µA
µA
mA
mA
µA
µA
mA
mA
%/V
%/V
mA/MHz
mA/MHz
mA/MHz
mA/MHz
Notes:
1. Given in Table 6.4 on page 52.
2. V_IO should not be lower than the V_DD voltage.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Guaranteed by characterization. Does not include oscillator supply current.
5. IDD estimation for different frequencies.
6. Idle IDD estimation for different frequencies.
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Rev. 1.1