C8051F54X_14 Datasheet, PDF (34/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
5.2. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the
repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output
conversion code is updated after each conversion. Inputs are measured from 0 to V_REF x 4095/4096. Data
can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.2). Unused
bits in the ADC0H and ADC0L registers are set to 0. Example codes are shown below for both right-justi-
fied and left-justified data.
Input Voltage
VREF x 4095/4096
VREF x 2048/4096
VREF x 2047/4096
0
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
0x0FFF
0x0800
0x07FF
0x0000
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0xFFF0
0x8000
0x7FF0
0x0000
When the ADC0 Repeat Count is greater than 1, the output conversion code represents the accumulated
result of the conversions performed and is updated after the last conversion in the series is finished. Sets
of 4, 8, or 16 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0CF register. The value must be right-jus-
tified (AD0LJST = 0), and unused bits in the ADC0H and ADC0L registers are set to 0. The following
example shows right-justified codes for repeat counts greater than 1. Notice that accumulating 2ⁿ samples
is equivalent to left-shifting by n bit positions when all samples returned from the ADC have the same
value.
Input Voltage
V_REF x 4095/4096
V_REF x 2048/4096
V_REF x 2047/4096
0
Repeat Count = 4
0x3FFC
0x2000
0x1FFC
0x0000
Repeat Count = 8
0x7FF8
0x4000
0x3FF8
0x0000
Repeat Count = 16
0xFFF0
0x8000
0x7FF0
0x0000
5.2.1. Settling Time Requirements
A minimum tracking time is required before an accurate conversion is performed. This tracking time is
determined by any series impedance, including the AMUX0 resistance, the ADC0 sampling capacitance,
and the accuracy required for the conversion.
Figure 5.5 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output,
use the settling time specified in Table 6.10. When measuring V_DD with respect to GND, R_TOTAL reduces to
R_MUX. See Table 6.9 for ADC0 minimum settling time requirements as well as the mux impedance and
sampling capacitor values.
t
=
ln


S^--2---A^{n--}

R_TOTALC_SAMPLE
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB).
t is the required settling time in seconds. R_TOTAL is the sum of the AMUX0 resistance and any external
source resistance. n is the ADC resolution in bits (10).
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