C8051F54X_14 Datasheet, PDF (147/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
18. Port Input/Output
Digital and analog resources are available through 25 (C8051F540/1/4/5) or 18 (C8051F542/3/6/7) I/O
pins. Port pins P0.0-P3.0 on the C8051F540/1/4/5 and port pins P0.0-P2.1 on the C8051F542/3/6/7 can
be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to
an analog function as shown in Figure 18.3. Port pin P3.0 on the C8051F540/1/4/5 can be used as GPIO
and is shared with the C2 Interface Data signal (C2D). Similarly, port pin P2.1 is shared with C2D on the
C8051F542/3/6/7. The designer has complete control over which functions are assigned, limited only by
the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Prior-
ity Crossbar Decoder. The state of a Port I/O pin can always be read in the corresponding Port latch,
regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 18.3 and Figure 18.4). The registers XBR0, XBR1, XBR2 are defined in SFR Definition 18.1 and
SFR Definition 18.2 and are used to select internal digital functions.
The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers
(PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Table 6.3 on
page 51.
XBR0, XBR1,
XBR2, PnSKIP
PnMDOUT,
PnDMIN Registers
2
Highest
UART0
Priority
4
SPI0
2
SMBus0
CP0
2
CP1
2
/SYSCLK
7
PCA0
Lowest
Priority
T0, T1,
4
/INT0,
/INT1
2
LIN0
25
Port
Latches
P0
P1 (Px.0-Px.7)
P2
P3
Priority
Decoder
8
Digital
Crossbar
8
8
8
P0
I/O
Cells
External
Pins
P0.0
P0.7
Highest
Priority
P1
I/O
Cells
P1.0
P1.7
P2
I/O
Cells
P3
I/O
Cell
PnMASK
PnMATCH
Registers
P2.0
P2.7
P3.0
Lowest
Priority
Figure 18.1. Port I/O Functional Block Diagram
Rev. 1.1
147