C8051F54X_14 Datasheet, PDF (259/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
0 00x0 x
R/W when
ARSEL = 1
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
R/W when
ARSEL = 0
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
Enable _{N-bit Comparator}
PCA0PWM
A EC
CC
R CO
LL
SOV
SS
EVF
EE
L
LL
10
x
Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
match _S SET _Q CEXn _Crossbar
Port I/O
R CLR Q
PCA Timebase
PCA0H:L
Overflow of N^th Bit
Figure 24.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
24.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 24.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Duty Cycle = -^--6---5----5---3---6-----^–-----P----C-----A----0----C----P-----n----^
65536
Equation 24.4. 16-Bit PWM Duty Cycle
Using Equation 24.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Rev. 1.1
259