C8051F54X_14 Datasheet, PDF (85/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
11. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization is shown in
Figure 11.1
PROGRAM/DATA MEMORY
(FLASH)
C8051F540/1/2/3
0xFF
0x3C00
0x3BFF
RESERVED
0x80
0x7F
16 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0x0000
0x1FFF
C8051F544/5/6/7
8 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Same 1024 bytes as
from 0x0000 to 0x03FF,
wrapped on 1024-byte
boundaries
0x0400
0x03FF
0x0000
XRAM
1K Bytes
(accessable using
MOVX instruction)
Figure 11.1. C8051F54x Memory Map
11.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F54x devices implement 16 kB or 8 kB
of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous
block from addresses 0x0000 to 0x3FFF in 16 kB devices and addresses 0x0000 to 0x1FFF in 8 kB
devices. The address 0x3BFF in 16 kB devices and 0x1FFF in 8 kB devices serves as the security lock
byte for the device. Addresses above 0x3BFF are reserved in the 16 kB devices.
Rev. 1.1
85