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C8051F54X_14 Datasheet, PDF (14/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family
C8051F54x
C2CK/RST
VREGIN
VDD
GND
VDDA
GNDA
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core (50 MHz)
16 kB Flash Program
Memory
256 Byte RAM
1 kB XRAM
Voltage Regulator
(LDO)
System Clock Setup
XTAL1 XTAL2
Internal Oscillator
(±0.5%)
External Oscillator
Clock Multiplier
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
SPI
I2C
Priority
Crossbar
Decoder
Crossbar Control
Analog Peripherals
Voltage
Reference VREF
VDD
VREF
12-bit
A
200ksps
ADC
M
U
X
VDD
VREF
P0 – P3
Temp
Sensor
GND
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Driver
CP0, CP0A +
Comparator 0 -
CP1, CP1A +
-
Comparator 1
Figure 1.1. C8051F540/1/4/5 Block Diagram
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
14
Rev. 1.1