C8051F54X_14 Datasheet, PDF (205/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
21. UART0
UART0 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated
baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide
range of baud rates (details in Section “21.1. Baud Rate Generator” on page 205). A received data FIFO
allows UART0 to receive up to three data bytes before data is lost and an overflow occurs.
UART0 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON0, SBRLH0, and
SBRLL0), two are used for data formatting, control, and status functions (SCON0, SMOD0), and one is
used to send and receive data (SBUF0). The single SBUF0 location provides access to both the transmit
holding register and the receive FIFO. Writes to SBUF0 always access the Transmit register. Reads of
SBUF0 always access the first byte of the Receive FIFO; it is not possible to read data from the
Transmit Holding Register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete). If additional bytes are available in the Receive FIFO, the RI0 bit cannot be cleared by software.
SYSCLK
Baud Rate Generator
SBRLH0 SBRLL0
Overflow
Timer (16-bit)
EN
Pre-Scaler
(1, 4, 12, 48)
SBCON0
Data Formatting
SMOD0
Control / Status
SCON0
TX
Logic
TX0
TX Holding
Register
SBUF0
RX FIFO
(3 Deep)
Write to SBUF0
Read of SBUF0
RX
Logic
RX0
UART0
Interrupt
Figure 21.1. UART0 Block Diagram
21.1. Baud Rate Generator
The UART0 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock
(SYSCLK) and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow for
a wide selection of baud rates over many clock frequencies.
The baud rate generator is configured using three registers: SBCON0, SBRLH0, and SBRLL0. The
UART0 Baud Rate Generator Control Register (SBCON0, SFR Definition 21.4) enables or disables the
baud rate generator and selects the prescaler value for the timer. The baud rate generator must be
enabled for UART0 to function. Registers SBRLH0 and SBRLL0 contain a 16-bit reload value for the dedi-
cated 16-bit timer. The internal timer counts up from the reload value on every clock tick. On timer over-
flows (0xFFFF to 0x0000), the timer is reloaded. The baud rate for UART0 is defined in Equation 21.1,
where “BRG Clock” is the baud rate generator’s selected clock source. For reliable UART operation, it is
recommended that the UART baud rate is not configured for baud rates faster than SYSCLK/16.
Rev. 1.1
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