C8051F54X_14 Datasheet, PDF (79/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 10.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
SETB C
Set Carry
1
1
SETB bit
Set direct bit
2
2
CPL C
Complement Carry
1
1
CPL bit
Complement direct bit
2
2
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
2
2
2
2
2
2
2
2
2
2
MOV bit, C
Move Carry to direct bit
2
2
JC rel
Jump if Carry is set
2
2/3*
JNC rel
Jump if Carry is not set
2
2/3*
JB bit, rel
Jump if direct bit is set
3
3/4*
JNB bit, rel
JBC bit, rel
Jump if direct bit is not set
Jump if direct bit is set and clear bit
3
3/4*
3
3/4*
Program Branching
ACALL addr11
Absolute subroutine call
2
3*
LCALL addr16
Long subroutine call
3
4*
RET
Return from subroutine
1
5*
RETI
Return from interrupt
1
5*
AJMP addr11
Absolute jump
2
3*
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
3
4*
2
3*
1
3*
2
2/3*
2
2/3
CJNE A, direct, rel
Compare direct byte to A and jump if not equal
3
4/5*
CJNE A, #data, rel
Compare immediate to A and jump if not equal
3
3/4*
CJNE Rn, #data, rel
Compare immediate to Register and jump if not 3
3/4*
equal
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
3
4/5*
equal
DJNZ Rn, rel
Decrement Register and jump if not zero
2
2/3*
DJNZ direct, rel
Decrement direct byte and jump if not zero
3
3/4*
NOP
No operation
1
1
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
Rev. 1.1
79