C8051F54X_14 Datasheet, PDF (114/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2
Bit
7
6
5
4
3
2
1
Name
PMAT
Type
R
R
R
R
R
R/W
R
Reset
0
0
0
0
0
0
0
SFR Address = 0xF7; SFR Page = 0x00 and 0x0F
Bit Name
Function
7:3 Unused Read = 00000b; Write = Don’t Care.
2 PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
1 Unused Read = 0b; Write = Don’t Care.
0 PREG0 Voltage Regulator Dropout Interrupt Priority Control.
This bit sets the priority of the Voltage Regulator Dropout interrupt.
0: Voltage Regulator Dropout interrupt set to low priority level.
1: Voltage Regulator Dropout interrupt set to high priority level.
0
PREG0
R/W
0
114
Rev. 1.1