C8051F54X_14 Datasheet, PDF (163/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.15. P0SKIP: Port 0 Skip
Bit
7
6
5
4
3
2
1
0
Name
P0SKIP[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD4; SFR Page = 0x0F
Bit
Name
Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 18.16. P1: Port 1
Bit
7
6
5
4
3
2
1
0
Name
P1[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x90; SFR Page = All Pages; Bit-Addressable
Bit Name
Description
Write
Read
7:0 P1[7:0] Port 1 Data.
0: Set output latch to logic 0: P1.n Port pin is logic
Sets the Port latch logic
LOW.
LOW.
value or reads the Port pin ^{1: Set output latch to logic 1: P1.n Port pin is logic}
logic state in Port cells con- ^HIGH.
HIGH.
figured for digital I/O.
Rev. 1.1
163