C8051F54X_14 Datasheet, PDF (164/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.17. P1MDIN: Port 1 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P1MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF2; SFR Page = 0x0F
Bit
Name
Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P1MDOUT register.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
SFR Definition 18.18. P1MDOUT: Port 1 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P1MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA5; SFR Page = 0x0F
Bit
Name
Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
164
Rev. 1.1