DS89C420-QCL Datasheet, PDF (96/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PARALLEL I/O
Each I/O port can be used as a general-purpose, bidirectional parallel I/O port. Data written to the port latch serves to set both the
level and the direction of the data on the pin. The output of the port pin is established by writing to the associated port pin latch. When
logic 0 is written to the port for output, the port is pulled to ground. When logic 1 is written to ports 1, 2, or 3, a strong driver momen-
tarily drives the pin from 0 to 1, and then a weak pullup maintains the 1. A logic 1 written to port 0 causes those pins to go tri-state,
functioning as open-drain outputs. A logic 1 in the port latch also configures the port pin to the input state. Since the pin is either weak-
ly pulled up or in three-state, the pin is the same as the driven logic state. The logic state of the pin itself does not alter the logic value
of the port latch.
PORT 0
This is an open drain, 8-bit, bidirectional, general-purpose I/O port. A reset condition or logic 1, written to the latches of this port, three-
state, the port pins. This condition also serves as an input mode. When used as an I/O port, external pullups are required. As an alter-
nate function, this port can be used as part of the multiplexed address/data bus to access external memory. Both nonpage and page
mode are supported. During the original 8051 expanded bus configuration (nonpage mode), when ALE is high, the LSB of the address
is presented to P0. When ALE is low, the port transitions to a bidirectional data bus. When used in page mode 1, P0 is used as the pri-
mary data bus only. When used in page mode 2, P0 is used for the LSB of the address only.
The use of port 0 as general-purpose I/O is not recommended if the device is used to access external memory. In this case, the state
of the pins are disturbed during the memory access. In addition, the pullups required to maintain a high state during the use as gen-
eral-purpose I/O interfere with the complementary drivers employed when the device operates as an expanded memory bus.
When port 0 is used as an address bus, the AD0-7 pins provide true drive capability for logic levels 1 and 0. No external pullups are
required. In fact, external pullups degrade the memory interface timing. A two-state system is used on AD0-7. This allows the pin to
be driven hard for a period of time, allowing the greatest possible setup or access time. The pin states are then held in a weak latch
until forced to the next state or overwritten by an external device. This assures a smooth transition between logic states and also allows
a longer hold time.
ADDRESS
A8-A15
ADDRESS
CONTROL
INTERNAL
DATA BUS
DQ
Q
WRITE
ENABLE
DELAY
= 2Tclk
VCC
VCC
PORT
2.n
VCC
READ
ENABLE
READ
LATCH/PIN
Figure 10-2. Port 2 Functional Circuitry
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