DS89C420-QCL Datasheet, PDF (60/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
OPTION CONTROL REGISTER BYTE
User-selectable options are present that must be set before beginning software execution. The option control register uses flash bits,
rather than SFRs, and is individually erasable and programmable as a byte-wide register. Bit 3 of this register is defined as the watch-
dog POR default. Setting this bit to 1 disables the watchdog reset function on power-up, and clearing this bit to 0 enables the watchdog
reset function automatically. Other bits of this register are undefined and are at logic 1 when read. The value of this register can be read
at address FCh in parallel programming mode or by executing the verify option control register instruction in ROM Loader mode.
Note: The hatched areas shown on the internal and external
memory are disabled on power-up (Default)
FFFF
FFFF
INTERNAL
REGISTERS
SCRATCH
PAD
128 Bytes SFR
FF
128 Bytes
Indirect
Addressing
80
7F
2F
20 ^{Bit Addressable}
1F
Bank 3
Bank 2
Bank 1
00
Bank 0
INTERNAL
MEMORY
03FF
1kB x 8
SRAM
Data OR
prog mem
addr from
0000
400–7FF
3FFF
4000
8kB x 8
Flash
Memory
(Program)
2000
1FFF
8kB x 8
Flash
Memory
(Program)
0000
0000
External
Program
Memory
External
Data
Memory
03FF
Non-usable if
Internal SRAM
0000 ^{is activated}
Figure 6-1. Memory Map for the DS89C420/430
INTERNAL SRAM MEMORY
The ultra-high-speed microcontroller incorporates an internal 1kB SRAM that is usable as data, program, or merged program/data mem-
ory. Upon a power-on reset, the internal 1kB memory is disabled and transparent to both program and data memory maps.
When used for data, the memory is addressed through MOVX commands, and is in addition to the 256 bytes of scratchpad memory.
To enable the 1kB SRAM as internal data memory, software must set the DME0 bit (PMR.0). After setting this bit, all MOVX accesses
within the first 1kB (0000h–03FFh) is directed to the internal SRAM. Any data memory accesses outside of this range are still directed
to the expanded bus. One advantage of using the internal data memory is that MOVX operations automatically default to the fastest
access possible. Note that the DME0 bit is cleared after any reset, so access to the internal data memory is prohibited until this bit is
modified. The contents of the internal data memory are not affected by the changing of the data memory enable (DME0) bit.
Table 6-2 shows how the DME1, DME0 bits affect the data memory map.
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