DS89C420-QCL Datasheet, PDF (101/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Table 11-1. Programmable Timers
BIT NAMES
GATE
C/T
M1, M0
TF0
TR0
T0M
T0MH
DESCRIPTION
Gate control enable for INT0 pin
Counter/timer select
Timer mode select bits
Timer overflow flag
Timer run control
Input clock select (/4)
Input clock high-speed select (/1)
Timer LSB
Timer MSB
REGISTER LOCATION
TMOD – 89h
TMOD – 89h
TMOD – 89h
TCON – 88h
TCON – 88h
CKCON – 8Eh
CKMOD – 96h
TL0 – 8Ah
TH0 – 8Ch
BIT POSITIONS
TMOD.3
TMOD.2
TMOD.1,0
TCON.5
TCON.4
CKCON.3
CKMOD.3
GATE
C/T
M1, M0
TF1
TR1
T1M
T1MH
Gate control enable for INT1 pin
Counter/timer select
Timer mode select bits
Timer overflow flag
Timer run control
Input clock select (/4)
Input clock high-speed select (/1)
Timer LSB
Timer MSB
TMOD – 89h
TMOD – 89h
TMOD – 89h
TCON – 88h
TCON – 88h
CKCON – 8Eh
CKMOD – 96h
TL1 – 8Bh
TH1 – 8Dh
TMOD.7
TMOD.6
TMOD.5,4
TCON.7
TCON.6
CKCON.4
CKMOD.4
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
T2OE
DCEN
T2M
T2MH
Timer overflow flag
Timer external flag
Timer 2 receive serial clock enable
Timer 2 transmit serial clock enable
External enable for T2EX pin
Timer run control
Counter/timer select
Capture/reload select
Output enable for T2 pin
Down count enable
Input clock select (/4)
Input clock high-speed select (/1)
Timer LSB
Timer MSB
Timer capture LSB
Timer capture MSB
T2CON – C8h
T2CON – C8h
T2CON – C8h
T2CON – C8h
T2CON – C8h
T2CON – C8h
T2CON – C8h
T2CON – C8h
T2MOD – C9h
T2MOD – C9h
CKCON – 8Eh
CKMOD – 96h
TL2 – CCh
TH2 – CDh
RCAP2L – CAh
RCAP2H – CBh
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
T2MOD.1
T2MOD.0
CKCON.5
CKMOD.5
TIMER 0, TIMER 1 MODES
Timers 0 and 1 both have three common operating modes. They are 13-bit timer/counter, 16-bit timer/counter, and 8-bit timer/counter
with autoreload. Timer 0 can additionally be configured to operate as two 8-bit timers. These four modes, controlled by the TMOD reg-
ister, are detailed in the following pages.
MODE 0
Mode 0 configures either timer 0 or timer 1 for operation as a 13-bit timer/counter. As shown in Figure 11-1, setting TMOD register bits
M1, M0 = 00b selects this operating mode for either timer 0 or timer 1.
When using timer 0, TL0 uses only bits 0 through 4. These bits serve as the 5 LSbs of the 13-bit timer. TH0 provides the 8 MSbs of the
13-bit timer. Bit 4 of TL0 is used as a ripple out to TH0 bit 0, thereby completely bypassing bits 5 through 7 of TL0. Once the timer is
started using the TR0 (TCON.4) timer enable, the timer counts as long as GATE (TMOD.3) is 0 or GATE is 1 and pin INT0 is 1. It counts
oscillator or system clock cycles if C/T (TMOD.2) is set to a logic 0 and 1 to 0 transitions on T0 (P3.4) if C/T is set to a 1. When the 13-
bit count reaches 1FFFh (all ones), the next count causes it to roll over to 0000h. The TF0 (TCON.5) flag is set and an interrupt occurs
if enabled. The upper 3 bits of TL0 are indeterminate.
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