DS89C420-QCL Datasheet, PDF (118/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Mode 1
Mode 1 is asynchronous and full duplex, using a total of 10 bits. The 10 bits consist of a start bit (logic 0), 8 data bits, and 1 stop bit
(logic 1) as illustrated in Figure 12-2. The data is transferred LSb first. As described above, the baud rates for mode 1 are generated
by either a divide-by-16 of timer 1 rollover, a divide-by-16 of the timer 2 rollover, or a divide-by-32 of timer 1 rollover. The UART begins
transmission after the first rollover of the divide-by-16 counter following a software write to SBUF. Transmission takes place on the TXD
pin. It begins by the start bit being placed on the pin. Data is then shifted out onto the pin, LSb first. The stop bit follows. The TI bit is
set by hardware after the stop bit is placed on the pin. All bits are shifted out at the rate determined by the baud-rate generator.
Once the baud-rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or SCON1.4) must be set to a logic 1
to allow reception. The falling edge of a start bit on the RXD pin begins the reception process. Data is shifted in at the selected baud
rate. At the middle of the stop bit time, certain conditions must be met to load SBUF with the received data:
• RI must = 0, and either
• If SM2 = 0, the state of the stop bit does not matter, or
• If SM2 = 1, the state of the stop bit must = 1.
If these conditions are true, then SBUF (hex address 99h or C1h) is loaded with the received byte, the RB8 bit (SCON0.2 or SCON1.2)
is loaded with the stop bit, and the RI bit (SCON0.0 or SCON1.0) is set. If these conditions are false, then the received data is lost
(SBUF and RB8 not loaded) and RI is not set. Regardless of the receive word status, after the middle of the stop bit time, the receiver
goes back to looking for a 1 to 0 transition on the RXD pin.
Each data bit received is sampled on the 7th, 8th, and 9th clock used by the divide-by-16 counter. Using majority voting, two equal
samples out of the three determine the logic level for each received bit. If the start bit was determined to be invalid ( = 1), then the
receiver goes back to looking for a 1 to 0 transition on the RXD pin in order to start the reception of data.
Mode 2
Mode 2 uses a total of 11 bits in asynchronous full-duplex communication, as illustrated in Figure 12-3. The 11 bits consist of 1 start
bit (a logic 0), 8 data bits, 1 programmable 9th bit, and one stop bit (a logic 1). Like mode 1, the transmissions occur on the TXD sig-
nal pin and receptions on RXD. For transmission purposes, the 9th bit can be stuffed as a logic 0 or 1. A common use is to put the par-
ity bit in this location. The 9th bit is transferred from the TB8 bit position in the SCON register (SCON0.3 or SCON1.3) during the write
to SBUF. Baud rates are generated as a fixed function of the crystal frequency, as described earlier in this section. Like mode 1, mode
2’s transmission begins after the first rollover of the divide-by-16 counter following a software write to SBUF. It begins by the start bit
being placed on the TXD pin. The data is then shifted out onto the pin LSb first, followed by the 9th bit, and finally the stop bit. The TI
bit (SCON0.1 or SCON1.1) is set when the stop bit is placed on the pin.
Reception begins when a falling edge is detected as part of the incoming start bit on the RXD pin. The RXD pin is then sampled accord-
ing to the baud-rate speed. The 9th bit is placed in the RB8 bit location in SCON (SCON0.2 or SCON1.2). When a stop bit has been
received, the data value is transferred to the SBUF receive register (hex address 99 or C1). The RI bit (SCON0.0 or SCON1.0) is set to
indicate that a byte has been received. At this time, the UART can receive another byte.
Once the baud-rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or SCON1.4) must be set to a logic 1
to allow reception. The falling edge of a start bit on the RXD pin begins the reception process. Data must be shifted in at the selected
baud rate. At the middle of the 9th bit time, certain conditions must be met to load SBUF with the received data.
• RI must = 0, and either
• If SM2 = 0, the state of the 9th bit does not matter, or
• If SM2 = 1, the state of the 9th bit must = 1.
If these conditions are true, then SBUF is loaded with the received byte, RB8 is loaded with the 9th bit, and RI is set. If these condi-
tions are false, then the received data is lost (SBUF and RB8 not loaded) and RI is set. Regardless of the receive word status, after the
middle of the stop bit time, the receiver goes back to looking for a 1 to 0 transition on RXD.
Data is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses the sample divide-
by-16 counter with either the oscillator divided by 2 or 4.
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