DS89C420-QCL Datasheet, PDF (33/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Serial Port Operation (in Oscillator Clocks)
SWB
Bit 5
CTM
Bit 4
4X/2X
Bit 3
ALEON
Bit 2
DME1, DME0
Bits 1, 0
4X/2X CD1:0
1
00
0
00
X
01
X
10
X
11
CLOCK (MODE 0)
SM2 = 0
3
6
12
12
3072
SM2 = 1
1
2
4
4
1024
CLOCK (MODE 2)
SMOD = 0 SMOD = 1
64
32
64
32
64
32
64
32
16384
8192
Switchback Enable. This bit allows an enabled external interrupt or serial port activity to force the
clock divide control bits to the divide-by-1 state (01b). Upon acknowledgement of an external
interrupt source, the device switches modes in order to service the interrupt. Note that this means
that an external interrupt must actually be recognized (i.e., be enabled and not masked by higher
priority interrupts) for the switchback to occur. For serial port reception, the switch occurs at the
start of the instructions following the falling edge of the start bit.
Crystal Multiplier Enable. This bit enables (= 1) or disables (= 0) the crystal multiplier function.
When set (= 1), the CKRY bit (EXIF.3) is cleared and the multiplier circuitry begins a stabilization
warm-up period to provide the clock multiplication factor specified by the 4X/2X bit (PMR.3). Upon
completion of the warm-up delay, the CKRY bit is set and the user can then modify CD1,CD0
(PMR.7, PMR.6) to select the crystal multiplier clock output. When clear (= 0), the crystal multipler
circuitry is disabled to conserve power. The CTM bit cannot be changed unless CD1,CD0 = 10b
and RGMD (EXIF.2) is cleared to 0. This bit is automatically cleared to 0 when the processor enters
stop mode.
Clock Multiplier Selection. This bit selects the clock multiplication factor as shown. 4X/2X = 0
The frequency multiplier is set to two times the incoming clock by 4X/2X = 0. 4X/2X = 1 sets the
frequency multiplier to 4 times the incoming clock. This bit can only be altered when the crystal
multiplier enable bit (CTM) is cleared. Therefore, it must be set for the desired multiplication factor
prior to setting the CTM bit.
ALE Enable. When set (= 1), this bit enables the ALE signal output during on-chip program and
data memory accesses. When clear (= 0), the ALE signal output is disabled during on-chip program
and data memory accesses. External memory access automatically enables ALE independent of
the state of ALEON.
Data Memory Enable 1-0. These bits determine the functional relationship of the first 1024 bytes
of data memory. Two memory configurations are supported to allow either external data memory
access through the expanded bus of port 0 and port 2, or internal SRAM data memory access.
Note these bits are cleared after a reset, so access to the internal SRAM is prohibited until these
bits are modified.
Data Memory Access
DATA MEMORY
DME1 DME0 ADDRESS
RANGE
MEMORY ACCESS
0
0
0000h–FFFFh External Data Memory (default)
X
1
0000h–03FFh Internal SRAM Data Memory
0400h–FFFFh External Data Memory
1
0
Reserved Reserved
Status Register (STATUS)
7
6
5
4
SFR C5
PIS2
PIS1
PIS0
—
R-0
R-0
R-0
R-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
3
SPTA1
R-0
2
SPRA1
R-0
1
SPTA0
R-0
0
SPRA0
R-0
PIS2-0
Bit 7, 6, 5
Priority Interrupt Status Bits 2-0. These bits indicate the level of interrupt that is
currently being serviced. (Interrupt levels 0-3 are associated with interrupt sources using the MP,LP
bits found in the IP1 and IP0 SFRS.)
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