DS89C420-QCL Datasheet, PDF (80/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
POWER MANAGEMENT SUMMARY
The following is a summary of the power management bits and those that are useful or related. They are contained in the register loca-
tions WDCON;D8h, EIE;E8h, EXIF;91h, and PCON; 87h.
WDCON.6 POR: Power-on reset. Hardware sets this bit on a power-up condition. Software can read it, but must clear it man-
ually. This bit assists software in determining the cause of a reset.
WDCON.5 EPFI: enable power-fail interrupt. Setting this bit to 1 enables the power-fail interrupt. This occurs when V_CC drops
to approximately 4.375V, and the processor vectors to location 33h. Setting this bit to a 0 turns off the power-fail interrupt.
WDCON.4 PFI: Power-fail interrupt flag. Hardware sets this bit to a 1 when a power-fail condition occurs. Software must clear the
bit manually. Writing a 1 to this bit forces an interrupt, if enabled.
WDCON.3
WDIF: Watchdog interrupt flag. If the watchdog interrupt is enabled (EIE.4), hardware sets this bit to indicate that
the watchdog interrupt has occurred. If the interrupt is not enabled, this bit indicates that the timeout has passed. If
the watchdog reset is enabled (WDCON.1), the user has 512 system clocks to strobe the watchdog prior to a reset.
Software or any reset can clear this flag.
WDCON.2
WTRF: Watchdog timer reset flag. Hardware sets this bit when the watchdog timer causes a reset. Software can read
it, but must clear it manually. A power-fail reset also clears the bit. This bit assists software in determining the cause of
a reset. If EWT = 0, the watchdog timer has no affect on this bit.
WDCON.1
EWT: Enable watchdog timer reset. Setting this bit turns on the watchdog timer reset function. The interrupt does not
occur unless the EWDI bit in the EIE register is set. A reset occurs according to the WD1 and WD0 bits in the CKCON
register. Setting this bit to a 0 disables the resets but leaves the timer running.
WDCON.0
RWT: Reset watchdog timer. This bit serves as the strobe for the watchdog function. During the timeout period, soft-
ware must set the RWT bit if the watchdog is enabled. Failing to set the RWT causes a reset when the timeout has
elapsed. There is no need to set the RWT bit to a 0 because it is self-clearing.
EIE.4
EWDI: Enable watchdog interrupt. Setting this bit in software enables the watchdog interrupt.
EXIF.0
BGS: Bandgap select. Setting this bit to a 1 allows the use of the bandgap voltage reference while in stop mode. Since
this function uses as much as 75µA, the bandgap is optional in stop mode. Setting this bit to a 0 turns off the bandgap
while in stop mode. When BGS = 0, no power-fail interrupt or power-fail reset is available in stop mode.
PCON.1
STOP. When this bit is set, the program stops execution, clocks are stopped, and the CPU enters power-down mode.
PCON.0
IDLE. Program execution halts, leaving timers, serial ports, and clocks running.
EXIF.2
RGMD: Ring oscillator mode. Hardware sets this status bit to a 1 when the clock source is the ring oscillator.
Hardware sets this status bit to a 0 when the crystal is the clock source. Refer to RGSL for operation of the ring oscil-
lator.
EXIF.1
RGSL: Ring oscillator select. When set to a 1 by software, the microcontroller uses a ring oscillator to come out of
stop mode without waiting for crystal startup. This allows an instantaneous startup when coming out of stop mode. It
is useful if software needs to perform a short task, and then return to stop. It is also useful if software must respond
quickly to an external event. After the crystal has performed 65,536 cycles, hardware switches to the crystal as its
clocksource. The RGMD status bit reports on this changeover. When RGSL is set to a 0, the microcontroller delays
software execution until after the 65,536 clock crystal startup time. RGSL is only cleared by a power-on reset and is
not altered by other forms of reset.
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