DS89C420-QCL Datasheet, PDF (102/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Note that when used as a timer, the input clock selection can be affected by the clock divide bits (PMR.7-6), the TxM bit (in the CKCON
register), and the TxMH bit (in the CKMOD register). The time base selection is described in more detail later in this section.
Mode 0 operates identically when timer 1 is used. The same information applies to TL1 and TH1, which form the 13-bit register. TR1
(TCON.6), INT1 (P3.3), T1 (P3.5) and the relevant C/T (TMOD.6), and GATE (TMOD.7) bits have the same functions.
MODE 1
Mode 1 configures the timer for 16-bit operation as either a timer or counter. Figure 11-1 shows that setting the TMOD select bits M1,
M0 = 01b invoke this operating mode. For timer n, all of the TLn and THn registers are used. For example, if timer 1 is configured in
mode 1, then TL1 holds the LSB and TH1 holds the MSB. Rollover occurs when the timer reaches FFFFh. An interrupt also occurs if
enabled and the relevant TFn flag is set. Time-base selection, counter/timer selection, and the gate function operate as described in
mode 0.
MODE 2
This mode configures the timer as an 8-bit timer/counter with automatic reload of the start value. This configuration is shown in Figure
11-2, and is selected when bits M1and M0 of the TCON register are set to 1 and 0, respectively. When configured in mode 2, the timer
uses TLn to count and THn to store the reload value. Software must initialize both TLn and THn with the same starting value for the first
count to be correct. Once the TLn reaches FFh, it is automatically loaded with the value in THn. The THn value remains unchanged
unless modified by software. Mode 2 is commonly used to generate baud rates since it runs without continued software intervention.
As in modes 0 and 1, mode 2 allows counting of either clock cycles or pulses on pin Tn (C/T = 1) when counting is enabled by TRn
and the proper setting of GATE and INTn pins.
EXTERNAL OSCILLATOR
INPUT TO TIMER
CLK MODE SYSCLK
DIVIDE-BY-1 OSC / 1
2X
OSC / 0.5
4X
OSC / 0.25
T0 = P3.4
(T1 = P3.5)
TR0 = TCON.4
(TR1 = TCON.6)
GATE = TMOD.3
(GATE = TMOD.7)
INT0 _{= P3.2}
( ^INT1 = P3.3)
DIVIDE-
BY-12
T0M = CKCON.3
(T1M = CKCON.4)
T0MH = CKMOD.3
0
(T1MH = CKMOD.4)
DIVIDE- 1
0
BY-4
C / T ^{= TMOD.2}
(C / T ^{= TMOD.6)}
TL0
1
0
(TL1)
CLK ₀
4
7
1
00 ^{MODE 0}
M1, M0 = TMOD.1,
TMOD.0
01
(M1, M0 = TMOD.5,
TMOD.4)
TH0
MODE 1
(TH1)
0
7
TF0 = TCON.5
(TF1 = TCON.7)
INTERRUPT
TIMER 1 FUNCTIONS
SHOWN IN PARENTHESES ()
NOTE: FOR POWER-MANAGEMENT MODE (DIVIDE-BY-1024) OPERATION, THE TIMER INPUT CLOCK TO THE TIMER IS
OSC / 1024 IF EITHER TXM = 1 OR TXMH = 1. OTHERWISE, THE TIMER INPUT IS OSC / 3072.
Figure 11-1. Timers/Counters 0 and 1, Modes 0 and 1
____________________________________________________________________________________________ 102