DS89C420-QCL Datasheet, PDF (65/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 2 BUS STRUCTURE
The page mode 2 external bus structure multiplexes the most significant address byte with data on P2 and uses P0 for the least sig-
nificant address byte. An illustration of this memory interface is provided in the Figure 6-6.
This bus structure speeds up external code fetches only. Aside from the different functions of P0 and P2 when operating in page mode
2, the external memory accesses are equal in duration and timing to those made in the nonpage mode. Figure 6-7 illustrates memory
cycles for the page mode 2 bus structure.
DATA MEMORY INTERFACE
As described in Section 4, the ultra-high-speed microcontroller provides a small amount of RAM mapped as registers for on-chip direct
access. This is not considered data memory and does not fall into the memory map. Systems that require more RAM or memory-
mapped peripherals must use the data memory area. This segment is a 64kB space located between 0000h and FFFFh. It is reached
PSEN
ALE
PORT 2
DS89C4x0
CK
74F373
LATCH
MSB ADDRESS ₍₈₎
DATA BUS
(8)
OE
64kB X 8
MEMORY
CE
PORT 0
Figure 6-6. Program Memory Interconnect (Page Mode 2)
LSB ADDRESS (8)
Internal Memory Cycles
XTAL1
ALE
PSEN
Port 0
Port 2
Ext Code Fetches
Page Miss
C1 C2 C3 C4
Page Hit
Page Hit
C1 C2 C1 C2
LSB Add
MSB Add
Data
LSB Add
LSB Add
Data
Data
Figure 6-7. Page Mode 2 External Code Fetch Cycle (CD1:0 = 10B)
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