DS89C420-QCL Datasheet, PDF (95/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
INTERRUPT LATENCY
Interrupt response time is normally between 4 and 18 memory cycles, depending on the state of the microcontroller when the interrupt
occurs. If the microcontroller is performing an ISR with equal or greater priority, interrupt latency increases because the new interrupt
is not invoked. In other cases, the response time depends on the current instruction. The fastest possible response to an interrupt is
four memory cycles. The four memory cycle response time includes one cycle for detecting the interrupt and three cycles to perform
the LCALL that is inherent in the interrupt request.
The maximum response time occurs if the microcontroller is performing a JBC instruction that clears a bit in IE, IP0, EIE, or EIP0, and
then executes a DIV as the next instruction. From the time an interrupt source is activated (not detected), the longest reaction time is
18 memory cycles. This includes one cycle to detect the interrupt, four cycles to finish the JBC, ten cycles to perform the DIV, then
three cycles for the LCALL to the ISR. This maximum response time of eighteen memory cycles assumes that there are no other pend-
ing interrupts of higher priority to be serviced and that the JBC instruction is not preceded and does not jump to any instruction that
aborts the priority decoding process (RETI or writes to IP0, IP1, EIP0, EIP1, IE, or EIE).
SECTION 10: I/O PORTS
The ultra-high-speed flash microcontroller provides 8-bit I/O ports. Each port appears as a special function register that can be
addressed as a byte or 8 individual bit locations. In general, the register and the port pin have identical values, and reading or writing
a port is the same as reading or writing the SFR for the port. The basic I/O driver function and its electrical characteristics are similar
to the drivers used in the DS87C520, with respect to individual port and pin conditions.
Port 0 and port 2 can serve either as general-purpose parallel I/O ports or as the expanded memory bus. Ports 1 and 3 can be used
as general-purpose parallel I/O ports with optional special functions associated with each pin. Enabling the special function for a pin
automatically converts the I/O pin to that function. An optional function of a pin can be turned on and off dynamically to suit the appli-
cation. Using one or more I/O pins of a port as special functions does not affect the remaining port pins. It should be noted that port
0 drivers are open-drain and require external pullups when used as general-purpose I/O ports.
ADDRESS\
DATA
EXTERNAL
ADDRESS
CONTROL
VCC
INTERNAL
DATA BUS
DQ
Q
WRITE
ENABLE
READ
ENABLE
Figure 10-1. Port 0 Functional Circuitry
READ
LATCH/PIN
PORT
0.n
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