DS89C420-QCL Datasheet, PDF (109/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Table 11-3. Timer 2 Baud-Rate Generation/Clock Output Mode
SYSTEM CLOCK MODE
Crystal multiply mode 4X
Crystal multiply mode 2X
Divide-by-1 (default)
Power management mode
(divide-by-1024)
PMR REGISTER BITS
4X/2X, CD1, CD0
100
000
X01, X10
X11
TIMER 2
BAUD-RATE GENERATION/CLOCK OUTPUT MODE
INPUT CLOCK FREQUENCY (TxMH, TxM = xx)
OSC / 2
OSC / 2
OSC / 2
OSC / 2048
WATCHDOG TIMER
The watchdog timer reset provides CPU monitoring by requiring software to clear the timer before the user-selected interval expires. If
the timer is not reset, the CPU can be reset by the watchdog. The watchdog function is optional and is described below.
The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an event timer, or a system super-
visor. As can be seen in Figure 11-9, the timer is driven by the main system clock that is supplied to a series of dividers. The divider
output is selectable, and determines the interval between timeouts. When the timeout is reached, an interrupt flag is set, and if enabled,
a reset occurs. The interrupt flag causes an interrupt to occur if its individual enable bit is set and the global interrupt enable is set.
The reset and interrupt are completely discrete functions that may be acknowledged or ignored, together or separately for various
applications.
The watchdog timer reset function works as follows. After initializing the correct timeout interval (discussed later), software first restarts
the watchdog using RWT (WDCON.0) and then enables, if desired, the reset function by setting the enable watchdog timer reset (EWT
= WDCON.1) bit. Any time prior to reaching its user-selected terminal value, software can set the reset watchdog timer (RWT =
WDCON.0) bit. If the watchdog timer is reset (RWT bit written to a logic 1) before the timeout period expires, the timer starts over.
Hardware automatically clears the RWT after software sets it.
XTAL1
RWT (WDCON.0)
(RESET WATCHDOG)
XTAL2
SYSTEM CLOCK _{DIVIDE-BY- DIVIDE-BY-}
MODE CONTROL
2¹⁷
2³
DIVIDE-BY- DIVIDE-BY-
2³
2³
WD1 (CKCON.7)
WD0 (CKCON.6)
SYSCLK OUTPUT
CLK MODE SYSCLK
DIVIDE-BY-1 OSC / 1
2X
OSC / 0.5
4X
OSC / 0.25
PMM
OSC / 1024
2¹⁷
2²⁰
2²³
2²⁶
TIMEOUT
TIMEOUT
SELECTOR
WDIF
(WDCON.3)
EWDI (EIE.4)
(ENABLE WATCHDOG TIMER)
512 SYSCLK
DELAY
EWT (WDCON.1)
(ENABLE WATCHDOG TIMER)
WATCHDOG
INTERRUPT
RESET
WTRF
(WDCON.2)
Figure 11-9. Watchdog Timer
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