DS89C420-QCL Datasheet, PDF (110/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
If the timeout is reached without RWT being set, hardware generates a watchdog interrupt if the interrupt source has been enabled. If
no further action is taken to prevent a watchdog reset in the 512 system clock cycles following the timeout, hardware has the ability to
reset the CPU if EWT = 1. When the reset occurs, the watchdog timer reset flag (WTRF = WDCON.2) is automatically set to indicate
the cause of the reset; however, software must clear this bit manually.
The watchdog timer is a free-running timer. When used as a simple timer with both the reset and interrupt functions disabled (EWT =
0 and EWDI = 0), the timer continues to set the watchdog interrupt flag each time the timer completes the selected timer interval as
programmed by WD1 (CKCON.7) and WD0 (CKCON.6). Restarting the timer using the RWT (WDCON.0) bit allows software to use the
timer in a polled timeout mode. The WDIF bit is cleared by software or any reset.
The watchdog interrupt is also available for applications that do not need a true watchdog reset, but a very long timer. The interrupt is
enabled using the enable watchdog timer interrupt (EWDI = EIE.4) bit. When the timeout occurs, the watchdog timer sets the WDIF bit
(WDCON.3), and an interrupt occurs if the global interrupt enable (EA = IE.7) is set. Note that WDIF is set 512 clocks before a poten-
tial watchdog reset. The watchdog interrupt flag indicates the source of the interrupt, and must be cleared by software.
Using the watchdog interrupt during software development can allow the user to select ideal watchdog reset locations. Code is first
developed without enabling the watchdog interrupt or reset functions. Once the program is complete, the watchdog interrupt function
is enabled to identify the required locations in code to set the RWT (WDCON.0) bit. Incrementally adding instructions to reset the watch-
dog timer prior to each address location (identified by the watchdog interrupt) allows the code to eventually run without receiving a
watchdog interrupt. At this point, the watchdog timer reset can be enabled without the potential of generating unwanted resets. At the
same time, the watchdog interrupt may also be disabled. Proper use of the watchdog interrupt with the watchdog reset allows inter-
rupt software to survey the system for errant conditions.
When using the watchdog timer as a system monitor, the watchdog reset function should be used. If the interrupt function were used,
the purpose of the watchdog would be defeated. For example, assume the system is executing errant code prior to the watchdog inter-
rupt. The interrupt would temporarily force the system back into control by vectoring the CPU to the interrupt service routine. Restarting
the watchdog and exiting by an RETI or RET would return the processor to the lost position prior to the interrupt. By using the watch-
dog reset function, the processor is restarted from the beginning of the program and, therefore, placed into a known state.
The watchdog timeout selection is made using bits WD1 (CKCON.7) and WD0 (CKCON.6). The watchdog has four timeout selections
based on the system clock frequency, as shown in the figure. Since the timeout is a function of the system clock, the actual timeout
interval is dependent on both the crystal frequency and the system clock mode. Shown in Table 11-4 is a summary of the selectable
watchdog timeout intervals for the various system clock modes and WD1:0 control bit settings. The watchdog reset, if enabled, is
always scheduled to occur 512 system clocks following the timeout. Watchdog-generated resets last for 13 oscillator cycles.
As discussed above, the watchdog timer has several SFR bits that contribute to its operation. It can be enabled to function as either
a reset source, interrupt source, software polled timer, or any combination of the three. Both the reset and the interrupt have status
flags. The watchdog also has a bit that restarts the timer. Table 11-5 shows the watchdog timer-related bits. Detailed bit descriptions
can be found in Section 4.
Table 11-4. Watchdog Timeout Intervals
SYSTEM CLOCK MODE
Crystal multiply mode 4X
Crystal multiply mode 2X
Divide-by-1 (default)
Power management mode
(divide-by-1024)
PMR REGISTER BITS
4X/2X, CD1, CD0
100
000
X01, X10
X11
WATCHDOG TIMEOUT
(IN NUMBER OF OSCILLATOR CLOCKS)
WD1:0 = 00b
2¹⁵
2¹⁶
2¹⁷
WD1:0 = 01b
2¹⁸
2¹⁹
2²⁰
WD1:0 = 10b
2²¹
2²²
2²³
WD1:0 = 11b
2²⁴
2²⁵
2²⁶
2²⁷
2³⁰
2³³
2³⁶
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