DS89C420-QCL Datasheet, PDF (86/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Table 7-3. Power Management and Status Bit Summary
BIT NAME
CD1, CD0
SWB
PIS2:PIS0
SPTA1
SPRA1
SPTA0
SPRA0
LOCATION
PMR.7–6
PMR.5
STATUS.7:5
STATUS.3
STATUS.2
STATUS.1
STATUS.0
FUNCTION
Clock divider control
CD1 CD0 osc cycles per system clock cycle
00
Crystal multiplier
01
Reserved
10
1 (reset default)
11
1024 (PMM)
Switchback enable
0 = Interrupts and serial port activity will not affect clock
divider control bits
1 = Enabled interrupts and serial port activity will cause a
switchback
Priority Interrupt Status
101 = Level 4 interrupt (power fail) in progress
100 = Level 3 interrupt in progress
011 = Level 2 interrupt in progress
010 = Level 1 interrupt in progress
001 = Level 0 interrupt in progress
000 = No interrupt in progress
Serial port 1 transmitter activity status
0 = Serial port 1 transmitter inactive
1 = Serial port 1 transmitter active
Serial port 1 receiver activity status
0 = Serial port 1 receiver inactive
1 = Serial port 1 receiver active
Serial port 0 transmitter activity status
0 = Serial port 0 transmitter inactive
1 = Serial port 0 transmitter active
Serial port 0 receiver activity status
0 = Serial port 0 receiver inactive
1 = Serial port 0 receiver active
RESET
STATE
10
0
0
0
0
0
0
READ/WRITE ACCESS
Write: 10 anytime;
00, 01, and 11 only when
previously in 10 state.
Unrestricted read.
Unrestricted
Read only
Read only
Read only
Read only
Read only
Power Management Mode Timing
The power management mode reduces power consumption by internally dividing the clock signal to the device, causing it to operate
at a reduced speed. When PMM is invoked, the external crystal continues to operate at full speed. The difference is that the device
uses 1024 external clocks to generate each system clock cycle as opposed to one clock per internal system clock cycle in the default
state. Relative timing relationships of all signals when the device is operating in PMM remains the same as the one cycle timing. Note
that all internal functions, on-board timers (including serial port baud-rate generation), watchdog timer, and software timing loops also
runs at the reduced speed. Most applications do not find it necessary to attend to this much detail, but the information is provided for
calculating critical timings. Figure 7-2 demonstrates the internal timing relationships during PMM.
PMM is entered and exited by setting the clock rate divider bits (PMR.7-6). In addition, it is possible use the switchback feature to effect
a return to the divide-by-1 mode from the power management mode. This allows both hardware and software to cause an exit from
PMM. Entry to or exit from PMM must be done through the divide-by-1 mode (CD1:0 = 10b). This means that to switch from divide-by-
1024 to the crystal multiplier 4X mode or vice versa, one must first switch back to divide-by-1 mode. Attempts to execute an illegal
speed change are ignored, and the bits remain unchanged. It is the responsibility of the software to test for serial port activity before
attempting to change speed, as a modification of the clock divider bits during a serial port operation corrupts the data.
_____________________________________________________________________________________________ 86