DS89C420-QCL Datasheet, PDF (58/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 6: MEMORY ACCESS
The ultra-high-speed flash microcontroller supports the memory interface convention established for the industry standard 80C51, but
also implements two new page mode memory interfaces needed to support ultra-high-speed external operation. These external page
mode interfaces are described later in this section.
Program and data memory areas can be implemented on-chip, off-chip, or as a combination. When opting not to use the internal mem-
ory provided, or when exceeding the maximum address of on-chip program or data memory, the device performs an external mem-
ory access using the expanded memory bus on ports 0 and 2. While serving as a memory bus, port 0 and port 2 cannot function as
I/O ports. The PSEN signal is driven active low to function as a chip enable or output enable when performing external code memory
fetches. The RD and WR signals serve as enables when accessing external SRAM data memory.
Program execution always begins at the reset vector, address 0000h. If on-chip program memory is enabled, program execution
begins at internal location 0000h; otherwise, external program memory is used. Any reset causes the next program fetch to begin at
this location. Subsequent branches and interrupts determine how program memory fetches deviate from sequential addressing.
INTERNAL FLASH MEMORY
The ultra-high-speed flash microcontroller contains five physically distinct blocks of embedded flash memory. The two largest blocks
are each half of the total amount of internal program memory. A 64-byte flash security block has been incorporated to allow encryp-
tion during program memory verify operations. To further protect internal code against undesirable access, a three-level lock system
has been implemented in a separate flash memory block. This single-byte block contains three lock bits (LB1, LB2, LB3), each of which
can individually enable higher lock levels and greater code protection. The fifth flash memory block is the option control register. This
byte contains a bit to enable or disable the watchdog timer reset function (EWT = WDCON.1) on a power-on reset.
The two program memory blocks form a contiguous address range extending from 0000h through the maximum amount of on-chip
program memory. The on-chip decoded address range is controlled in hardware by the EA pin, and in software through the ROMSIZE
feature. The EA pin enables or disables the ability to access internal program memory and overrides any software configured bit set-
tings. The logic state of the EA pin should be changed only when the microcontroller is being held in reset. The EA pin is sampled on
each exit from the reset state to determine whether program fetching should begin internally or externally. When the EA pin is low, all
code fetches are done externally through the expanded bus. When the EA pin is high, code fetches begin from internal program mem-
ory. Code fetches exceeding the maximum address of on-chip program memory cause the device to access off-chip program memo-
ry. The maximum on-chip decoded address is selectable by software using the ROMSIZE feature.
ROMSIZE FEATURE
Using the ROMSIZE feature, software can imitate a device with less on-chip memory. The maximum memory size is dynamically vari-
able. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then restored to access on-chip
memory. In fact, all of the on-chip memory can be removed from the memory map, allowing the full 64kB of external memory space to
be addressed.
The ROMSIZE feature has two primary uses. In the first instance, it allows the device to act as a bootstrap loader for a flash memory
or nonvolatile SRAM (NVSRAM). The internal program memory can contain a bootstrap loader, which can program the external mem-
ory device. Secondly, this method can be used to increase the amount of available program memory from 64kB to 80kB without bank
switching.
The maximum amount of on-chip memory is selected by configuring the ROM size select register bits RMS2, RMS1, RMS0 (ROM-
SIZE.2-0). The reset default condition gives access to the maximum on-chip program memory. In this configuration, only code address-
es greater than the maximum amount of on-chip program memory result in external program memory accesses. The possible settings
for the ROM size select register are shown in the ROMSIZE special-function register.
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