DS89C420-QCL Datasheet, PDF (59/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Modification of the ROMSIZE (C2h) special function register requires using the timed access procedure and must be followed by a two
machine cycle delay, such as executing two NOP instructions, before jumping to the new address range. Interrupts must be disabled
during this operation, because a call to an interrupt vector during the changing of the memory map can cause erratic results. To select
a different internal program memory size, software must alter bits RMS2–RMS0. The procedure to reconfigure the size of on-chip mem-
ory should be done as follows:
1) Jump to a location in program memory that is unaffected by the change.
2) Disable interrupts by clearing the EA bit (IE.7).
3) Write AAh to the timed access register (TA;C7h).
4) Write 55h to the timed access register (TA;C7h).
5) Modify the ROM size select bits (RMS2-RMS0).
6) Delay 2 machine cycles (2 NOP instructions).
7) Enable interrupts by setting the EA bit (IE.7).
As noted in the first step above, ensure that changes to the ROMSIZE register do not corrupt program execution. For example, assume
that a 16kB DS89C430 is executing instructions from internal program memory near the 12kB boundary (~3000h) and the ROMSIZE
register is still configured to the default internal program space. If software reconfigures the ROMSIZE register for a maximum of 4kB
(0000h–0FFFh) internal program space (RMS2–0 = 011b), the device immediately accesses external program memory since current
program execution no longer resides within the new on-chip decoded range. This could result in code misalignment and execution of
an invalid instruction. The recommended method is to modify the ROMSIZE register from a location in memory that is internal (or exter-
nal) both before and after the operation. In the above example, the instruction which modifies the ROMSIZE register should be locat-
ed below the 4kB (1000h) boundary or above the maximum boundary, so that it is unaffected by the memory modification. The same
rule applies when executing from external program memory and increasing the on-chip decoded address range.
If the 0kB of internal program memory setting is selected, take extra precautions. In this case, it is necessary to duplicate the interrupt
vector table in external program memory. This is because the interrupt vector table is located in the lower 1kB of memory, and the
device automatically redirects any fetches from the interrupt vector table to external memory. Be careful when assembling or compil-
ing the program so that all the modules are located at the correct starting address, including the interrupt vector table.
FLASH SECURITY BLOCK/LOCK BITS
The device incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing the data in encrypted form.
The encryption array, often referred to as the security block, has the same electrical and timing characteristics as the on-chip program
memory. Once the encryption array is programmed to non-FFh, the data presented in the verify mode is encrypted. Each byte of data
is XNORed with a byte in the encryption array during verification. If the security block is used, program unused portions of the internal
flash program memory range with random data so that the encryption vector cannot be easily extracted.
The single byte, which contains the 3 lock bits, logically resides at byte address 40h of the security block. The 3 lock bits (LB3, LB2,
and LB1) can be accessed in bit positions 5, 4, and 3, respectively. By programming the 3 lock bits, the user may select a level of
security as specified in table below. Once a security level is selected and programmed, the setting of the lock bits remains. Only a
mass erase erases these bits and allows reprogramming the security level to a less restricted protection.
Table 6-1. Flash Memory Lock Bits
LEVEL
LB1
LB2
LB3
PROTECTION
1
1
1
1
No program lock. Encrypted verify if encryption array is programmed.
Prevent MOVC in external memory from reading program code in internal memory.
2
0
1
1
EA is sampled and latched on reset. Allow no further parallel or program memory
Loader programming.
3
X
0
1
Level 2 plus no verify operation. Also prevent MOVX in external memory from
reading internal SRAM.
4
X
X
0
Level 3 plus no external execution.
The lock bits affect the read/write accessibility in program memory loader and parallel programming modes.
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