DS89C420-QCL Datasheet, PDF (47/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 10b (FOUR CYCLES)
The page mode 1 external bus structure multiplexes port 2 to provide the address MSB and LSB. Data transactions occur exclusive-
ly on port 0. ALE is used to latch the address MSB only when needed, and PSEN serves as the enable for external program memory.
Page mode 1 must be initiated by internal code memory. To invoke 4-cycle page mode 1 operation, the PAGES1:0 bits must be set to
10b, followed by the setting of the PAGEE bit. In the four-cycle page mode 1 configuration, a page-hit memory cycle is four system
clocks in length, while the page-miss memory cycle requires eight system clocks.
The first diagram below shows the fetch of the DA A instruction (1 byte, two cycles) during a page-miss memory cycle as would occur
when a page boundary is crossed. Like nonpage mode operation, a “dummy” or stall cycle must then be inserted for the single-byte
DA A instruction, since it requires two cycles of execution time. After stalling for one cycle, the real fetch of the RRC A instruction takes
place.
The second diagram below illustrates the fetch of the DA A instruction as the last byte of a 256-byte page. In this case, the stall cycle
needed in executing the DA A instruction coincides with a page-miss memory cycle instead of a page hit (as in the first diagram).
FOUR-CYCLE PAGE MODE 1: (PAGE MISS) – DA A – RRC A
SYSCLK
ALE
PSEN
PORT 2
MSB ADDRESS
MISS
LSB ADDRESS
STALL
HIT
LSB ADDRESS
PORT 0
D4
13
13
HIT
LSB ADDRESS
DA A
NONPAGE MODE: DA A – (PAGE MISS) – RRC A
SYSCLK
ALE
PSEN
PORT 2
HIT
LSB ADDRESS
STALL
MSB ADDRESS
MISS
LSB ADDRESS
PORT 0
D4
13
HIT
LSB ADDRESS
13
RRC A
HIT
LSB ADDRESS
DA A
RRC A
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