DS89C420-QCL Datasheet, PDF (26/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Address Control (ACON)
7
6
5
4
3
2
1
0
SFR 9Dh
PAGEE
PAGES1
PAGES0
—
—
—
—
—
RT-0
RT-0
RT-0
R-1
R-1
R-1
R-1
R-1
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset
PAGEE
Page Mode Enable. When set (= 1), page mode access is enabled for external bus operations
Bits 7
as configured by the page mode select bits PAGES1, PAGES0. When clear (= 0), external bus
operations default to the standard 8051 expanded bus configuration.
PAGES1, PAGES0
Bits 6, 5
Page Mode Select. If PAGEE = 1, these bits select the page mode configuration that is followed
for external bus operations. The four possible configurations are summarized in the table below.
Mode 1 results in Port 0 serving as the data bus and Port 2 being the multiplexed address
MSB/LSB. Mode 2 results in Port 0 being used strictly for address LSB and Port 2 being multiplexed
between address MSB and data.
Memory Access Cycle
PAGES 1-0
00
01
10
11
MODE
1
1
1
2
PAGE-HIT
1
2
4
2
PAGE-MISS
2
4
8
4
Bits 4–0
Port 2 (P2)
Reserved. Read data is 1.
7
6
5
SFR A0h
P2.7
P2.6
P2.5
RW-1
RW-1
RW-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
P2.4
RW-1
3
P2.3
RW-1
2
P2.2
RW-1
1
P2.1
RW-1
0
P2.0
RW-1
P2.7–0
Bits 7–0
Port 2. This port functions according to the table below where PAGEE = ACON.7 and PAGES =
ACON.6-5.
Port 2 Functions
PAGEE
0
0
1
1
PAGES
XX
XX
00, 01, 10
11
PORT2 FUNCTION
General-Purpose I/0 (code execution < ROMSIZE.2-0)
Address MSB (code execution > ROMSIZE.2-0)
Multiplexed Address MSB/LSB
Multiplexed Address MSB/Data
Writing a 1 to an SFR bit configures the associated port pin as an input. All read operations, with
the exception of read-modify-write instructions, leave the port latch unchanged. During external
memory addressing and data memory write cycles, the port has high and low drive capability.
During external memory data read cycles, the port is held in a high-impedance state.
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