DS89C420-QCL Datasheet, PDF (21/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Timer 0 LSB (TL0)
7
6
5
4
3
2
1
SFR 8Ah
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
TL0.7–0
Bits 7–0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
Timer 1 LSB (TL1)
0
TL0.0
RW-0
7
6
5
SFR 8Bh
TL1.7
TL1.6
TL1.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
TL1.4
RW-0
3
TL1.3
RW-0
2
TL1.2
RW-0
1
TL1.1
RW-0
TL1.7–0
Bits 7–0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
Timer 0 MSB (TH0)
0
TL1.0
RW-0
7
6
5
SFR 8Ch
TH0.7
TH0.6
TH0.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
TH0.4
RW-0
3
TH0.3
RW-0
2
TH0.2
RW-0
1
TH0.1
RW-0
TH0.7–0
Bits 7–0
Timer 1 MSB (TH1)
Timer 0 MSB. This register contains the most significant byte of Timer 0.
0
TH0.0
RW-0
7
6
5
SFR 8Dh
TH1.7
TH1.6
TH1.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
TH1.4
RW-0
3
TH1.3
RW-0
2
TH1.2
RW-0
1
TH1.1
RW-0
TH1.7–0
Bits 7–0
Timer 1 MSB. This register contains the most significant byte of Timer 1.
0
TH1.0
RW-0
Clock Control (CKCON)
7
6
5
SFR 8Eh
WD1
WD0
T2M
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
T1M
RW-0
3
T0M
RW-0
2
MD2
RW-0
1
MD1
RW-0
0
MD0
RW-1
WD1, WD0
Bits 7, 6
Watchdog Timer Mode Select 1-0. These bits determine the watchdog timer timeout period for
the watchdog timer. The timer divides the crystal (or external oscillator) frequency by a program-
mable value as shown on the next page. The divider value is expressed in crystal (oscillator)
cycles. The settings of the system clock control bits 4X/2X (PMR.3) and CD1:0 (PMR.7-6) affect the
clock input to the watchdog timer and therefore its timeout period as shown below. All watchdog
timer reset timeouts follow the setting of the interrupt flag by 512 system clocks.
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