DS89C420-QCL Datasheet, PDF (44/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
MUX
00
01, 10
11
SYSTEM
CLOCK
EXECUTION
INTERNAL
EXTERNAL
NON PAGE
PAGE MODE 1 (1-CYCLE)
PAGE MODE 1 (2-CYCLE)
PAGE MODE 1 (3-CYCLE)
PAGE MODE 2
MEMORY CYCLE
SYSCLK/1
SYSCLK/4
SYSCLK/1
SYSCLK/2
SYSCLK/4
SYSCLK/2 (PROG)
SYSCLK/4 (DATA)
MEMORY
CYCLE
Figure 5-4. Instruction Memory Cycle Determination
INSTRUCTION TIMING
The ultra-high-speed microcontroller executes the industry standard 8051 instruction set. Each instruction requires a minimum of one
memory cycle of execution time, and may require as many as ten memory cycles (DIV AB only). The number of memory cycles required
to execute any given 8051 instruction is documented at the end of this section and can be found in Section 14 (Instruction Set Details).
A memory cycle is the basic timing unit for the ultra-high-speed microcontroller. If internal program code is being executed, a memo-
ry cycle always consists of one system clock. If external program code is being executed, a memory cycle is then composed of 1, 2,
or 4 system clocks, as defined by the external bus configuration (non page mode, page mode 1, or page mode 2).
Calculating the number of external crystal or oscillator clock periods (tCLCL) per memory cycle additionally depends upon how the
user has configured the system clock as a function of the external clock. The system clock control function was covered earlier in the
section. As an example, if the crystal multiplier is used to generate a system clock frequency four times the frequency of the external
clock source, a nonpaged mode external memory cycle would consist of one external clock.
All instructions are coded within an 8-bit field called an op code. This single byte must be fetched from program memory. The CPU
decodes the op code to determine what action the microcontroller must take or whether additional information is needed from memo-
ry. If no other memory is needed, then only 1 byte was required. Thus, the instruction is called a 1-byte instruction. In some cases,
more data is needed. These are 2- or 3-byte instructions.
Single-Byte Instructions
A single-byte instruction can require anywhere between one and ten memory cycles to execute. When the execution cycle count
exceeds the byte count, the program counter must stall until instruction execution is completed. All MOVX data memory access instruc-
tions have a single-byte op code, but require more memory cycles so that data may be accessed. The MOVX instruction timing is cov-
ered in Section 6 (Memory Access). Following are examples of single byte instructions, each requiring a different number of execution
cycles:
RRC A
DA A
RET
MUL AB
DIV AB
OPCODE
13h
D4h
22h
A4h
84h
NO. OF CYCLES
1
2
3
9
10
2-Byte Instructions
All 2-byte instructions require a minimum of two cycles, since fetching each byte requires a separate memory access. The first byte is
the instruction op code that is decoded by the CPU. The second byte is normally an operand, or it can specify the location of the
operand. For example, “ADD A, direct” is a 2-byte, two cycle instruction where the second byte specifies the direct address location
of the operand. Due to internal access restrictions, certain direct addressing instructions require one extra memory cycle when oper-
ating on the PSW, SP, DPS, IE, EIE, IP0, IP1, EIP0, or EIP1 register. Following are examples of these and other 2-byte instructions:
ADD A, direct
ADD A, #data
SJMP rel
OPCODE
25h
24h
80h
OPERAND/LOCATION
<addr7-0>
<data7-0>
<addr7-0>
NO. OF CYCLES
2
2
3
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