DS89C420-QCL Datasheet, PDF (94/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
INTERRUPT ACKNOWLEDGE CYCLE
The process of acknowledging an interrupt begins with the setting of the associated flag. For edge-triggered external interrupts and
internal interrupt sources, the interrupt flags are set automatically by hardware. For level-sensitive external interrupts, the flags are actu-
ally under control of the external signal, and the flag rises and falls with the pin level. All interrupt flags are evaluated on the final exe-
cution cycle of each instruction. A priority decoding process is performed among pending and new interrupt sources in order to select
the appropriate interrupt vector address. This decoding process is accomplished in a single memory cycle using combinatorial logic.
Hardware then forces an LCALL to the selected vector address in the following memory cycle, unless blocked by one of the following
conditions:
• An interrupt of equal or greater priority has already been invoked and the RETI instruction has not been issued to terminate it,
• The current cycle is not the final cycle in the execution of the current instruction, or
• The instruction in progress is an RETI or a write to IP0, IP1, EIP0, EIP1, IE, or EIE.
INTERRUPT
FLAG
BITS
INTERRUPT
ENABLE BITS
INTERRUPT SELECTION
PRIORITY BITS HARDWARE
HIGHEST
PFI
PRIORITY
INT0
TF0
INT1
IT1
TF1
RI 0
TI_0
TF2
EXF2
RI_1
TI 1
INT2
INTERRUPT
VECTOR
INT3
INT4
INT5
WATCHDOG
Figure 9-1. Interrupt Functional Description
INDIVIDUAL GLOBAL
ENABLES ENABLE
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