DS89C420-QCL Datasheet, PDF (30/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Least Significant Priority Select Bit Levels
MP (IP1.X)
0
0
1
1
LP (IP0.X)
0
1
0
1
Slave Address Mask Enable Register 0 (SADEN0)
PRIORITY LEVEL
0 (natural priority)
1
2
3 (high priority)
7
6
5
SFR B9h
SADEN0.7 SADEN0.6 SADEN0.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
SADEN0.4
RW-0
3
SADEN0.3
RW-0
2
SADEN0.2
RW-0
1
SADEN0.1
RW-0
0
SADEN0.0
RW-0
SADEN0.7–0
Bits 7–0
Slave Address Mask Enable Register 0. This register functions as a mask when comparing
serial port 0 addresses for automatic address recognition. When a bit in this register is set, the
corresponding bit location in the SADDR0 register is exactly compared with the incoming serial
port 0 data to determine if a receiver interrupt should be generated. When a bit in this register is
cleared, the corresponding bit in the SADDR0 register becomes a “don’t care” and is not com-
pared against the incoming data. All incoming data generates a receiver interrupt when this reg-
ister is cleared.
Slave Address Mask Enable Register 1 (SADEN1)
7
6
5
SFR BAh
SADEN1.7
SADEN1.6
SADEN1.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
SADEN1.4
RW-0
3
SADEN1.3
RW-0
2
SADEN1.2
RW-0
1
SADEN1.1
RW-0
0
SADEN1.0
RW-0
SADEN1.7–0
Bits 7–0
Slave Address Mask Enable Register 1. This register functions as a mask when comparing
serial port 1 addresses for automatic address recognition. When a bit in this register is set, the
corresponding bit location in the SADDR1 register is exactly compared with the incoming serial
port 1 data to determine if a receiver interrupt should be generated. When a bit in this register is
cleared, the corresponding bit in the SADDR1 register becomes a “don’t care” and is not compared
against the incoming data. All incoming data generates a receiver interrupt when this register is
cleared.
Serial Port 1 Control (SCON1)
7
6
5
SFR C0h
SM0/FE_1
SM1_1
SM2_1
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
REN_1
RW-0
3
TB8_1
RW-0
2
RB8_1
RW-0
1
TI_1
RW-0
0
RI_1
RW-0
SM0–2
Bits 7, 6, 5
Serial Port 1 Mode. These bits control the mode of serial port 1 as shown in the following table.
In addition, the SM0 and SM2 bits have secondary functions as shown.
Serial Port 1 Modes and Functions
SM0
0
0
0
1
1
1
1
SM1
0
0
1
0
0
1
1
SM2
0
1
X
0
1
0
1
MODE
0
0
1
2
2
3
3
FUNCTION
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous with multiprocessor
communication
Asynchronous
Asynchronous with multiprocessor
communication
LENGTH (BITS)
8
8
10
11
PERIOD
See PMR register
See PMR register
Timer 1 or 2 baud rate equation
See PMR register
11
See PMR register
11
Timer 1 or 2 baud rate equation
11
Timer 1 or 2 baud rate equation
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