DS89C420-QCL Datasheet, PDF (46/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
NONPAGE MODE EXTERNAL TIMING (CONTINUED)
The first diagram below illustrates an ACALL instruction (2 bytes, two cycles) with a destination address residing on a different 256-
byte page. This is indicated only by the MSB address change on port 2. The memory cycle duration remains constant.
The second diagram below shows execution of the RET instruction (1 byte, three cycles). Because the cycle count of the RET instruc-
tion exceeds the byte count, two stall cycles (“dummy” fetches) are inserted to allow execution to complete. In this example, the return
address and the RET instruction are on different 256-byte pages (signified by the MSB address change on port 2).
NONPAGE MODE: ACALL – NOP
SYSCLK
ALE
PSEN
PORT 2
MSB ADDRESS
PORT 0
LSB
71
LSB
33
LSB
ACALL
NONPAGE MODE: RET – NOP
SYSCLK
ALE
PSEN
PORT 2
MSB ADDRESS
PORT 0
LSB
22
LSB
LSB
RET
MSB ADDRESS
00
LSB
NOP
MSB ADDRESS
LSB
00
LSB
NOP
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