DS89C420-QCL Datasheet, PDF (23/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Port 1 (P1)
7
6
5
4
3
2
1
0
SFR 90h
P1.7
INT5
P1.6
INT4
P1.5
INT3
P1.4
INT2
P1.3
TXD1
P1.2
RXD1
P1.1
T2EX
P1.0
T2
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
P1.7–0
Bits 7–0
General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all
the pins have an alternative function listed below. Each of the functions is controlled by several
other SFRs. The associated Port 1 latch bit must contain a logic 1 before the pin can be used in its
alternate function capacity.
INT5
Bit 7
External Interrupt 5. A falling edge on this pin causes an external interrupt 5 if enabled.
INT4
Bit 6
External Interrupt 4. A rising edge on this pin causes an external interrupt 4 if enabled.
INT3
Bit 5
External Interrupt 3. A falling edge on this pin causes an external interrupt 3 if enabled.
INT2
Bit 4
External Interrupt 2. A rising edge on this pin causes an external interrupt 2 if enabled.
TXD1
Bit 3
Serial Port 1 Transmit. This pin transmits the serial port 1 data in serial port modes 1, 2, 3 and
emits the synchronizing clock in serial port mode 0.
RXD1
Bit 2
Serial Port 1 Receive. This pin receives the serial port 1 data in serial port modes 1, 2, 3 and is a
bidirectional data transfer pin in serial port mode 0.
T2EX
Bit 1
Timer 2 Capture/Reload Trigger. A 1-to-0 transition on this pin causes the value in the T2
registers to be transferred into the capture registers if enabled by EXEN2 (T2CON.3). When in auto-
reload mode, a 1-to-0 transition on this pin reloads the Timer 2 registers with the value in RCAP2L
and RCAP2H if enabled by EXEN2 (T2CON.3).
T2
Timer 2 External Input. A 1-to-0 transition on this pin causes Timer 2 increment or decrement bit
External Interrupt Flag (EXIF)
7
6
5
4
3
2
1
SFR 91h
IE5
IE4
IE3
IE2
CKRY
RGMD
RGSL
RW-0
RW-0
RW-0
RW-0
R-*
R-*
RW-*
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset,* = See description.
0
BGS
RT-0
Bit 0
IE5
Bit 7
IE4
Bit 6
IE3
Bit 5
IE2
Bit 4
CKRY
Bit 3
depending on the timer configuration.
External Interrupt 5 Flag. This bit is set when a falling edge is detected on INT5. This bit must
be cleared manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 4 Flag. This bit is set when a rising edge is detected on INT4. This bit must
be cleared manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 3 Flag. This bit is set when a falling edge is detected on INT3. This bit must
be cleared manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 2 Flag. This bit is set when a rising edge is detected on INT2. This bit must
be cleared manually by software. Setting this bit in software causes an interrupt if enabled.
Clock Ready. This bit indicates the status of the startup period for the crystal oscillator or crystal
multiplier warm-up period. This bit is cleared after a reset or when exiting STOP mode. It is also
cleared when the clock multiplier is enabled (setting of PMR.4 = 1). Once CKRY is cleared, a
65,536 clock count must take place before CKRY is set and the lockout preventing modification of
CD1:CD0 is removed. Once CKRY is set (= 1), the clock multiplier can then be selected as the
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