DS89C420-QCL Datasheet, PDF (49/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 10b (FOUR CYCLES)
(CONTINUED)
The two diagrams below demonstrate the execution of the RET (1 byte, three cycles) instruction. In the first diagram, the return address resides on
the same 256-byte page as that of the executed RET instruction. Two stall cycles are inserted followed by a page-hit memory cycle. In the second
diagram, the return address is on a different 256-byte page from where the RET instruction was executed. In this case, two stall cycles are inserted,
followed by a page-miss memory cycle.
FOUR-CYCLE PAGE MODE 1: RET
SYSCLK
ALE
PSEN
PORT 2
HIT
LSB ADDRESS
PORT 0
22
STALL
STALL
LSB ADDRESS
HIT
LSB ADDRESS
HIT
LSB ADDRESS
RET
FOUR-CYCLE PAGE MODE 1: RET – (PAGE MISS)
SYSCLK
ALE
PSEN
PORT 2
HIT
LSB ADDRESS
STALL
STALL
LSB ADDRESS
PORT 0
22
MISS
MSB ADDRESS
LSB ADDRESS
ACALL
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