DS89C420-QCL Datasheet, PDF (87/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
MINIMUM INSTRUCTION CYCLE
INTERNAL
SYSTEM
CLOCK
(PMM)
EXTERNAL
CLOCK
1024 CLOCKS
Figure 7-3. Internal Timing Relationships in PMM
PMM and Peripheral Functions
Timers 0, 1, and 2 default on reset to a 12 clock per cycle operation to remain compatible with the original 8051 timing. The timers can
be individually configured to run at the fastest instruction cycle timing (divide-by-1) or to a system clock divide-by-4 input by setting
the relevant bits in the clock control register (CKCON;8Eh). Because the timers derive their time base from the internal clock, timers 0,
1, and 2 operate at reduced clock rates during PMM. This also affects the operation of the serial ports in PMM. In general, it is not pos-
sible to generate standard baud rates while in PMM, and the user is advised to avoid PMM, or use the switchback feature, if serial port
operation is desired. Table 7-4 shows the effect of the PMM clock divider option on timer and serial port operation.
Table 7-4. Effect of PMM Clock Mode on Timer, Serial Operation
CD1:0
11
OSC
CYCLES PER
MACHINE
CYCLE
1024
OSC CYCLES
PER TIMER
0/1/2 CLOCK
TxMH, TxM =
00
01
1x
3072
1024
1024
OSC CYCLES
PER TIMER 2
CLOCK, BAUD-
RATE GEN.
TxMH, TxM =
xx
2048
OSC CYCLES
PER SERIAL
PORT CLOCK
MODE 0
SM2 =
0
1
3072
1024
OSC CYCLES PER
SERIAL
PORT CLOCK
MODE 2
SMOD =
0
1
16,348
8192
SWITCHBACK
The switchback feature solves one of the most vexing problems faced by power-conscious systems. Many applications are unable to
use the stop and idle modes because they require constant computation. Traditionally, system designers could not reduce the oper-
ating speed below that required to process the fastest event. This meant that system architects would be forced to operate their sys-
tems at the highest rate of speed, even when it was not required. The switchback feature allows a system to operate at a relatively slow
speed and burst to a faster mode when required by an external event. When this feature is enabled by setting the switchback enable
bit (SWB), (PMR.5), a qualified interrupt, serial port reception, or transmission causes the device to return to the default divide-by-1
mode. A qualified interrupt is defined as an interrupt that has occurred and been acknowledged. This means that an interrupt must be
enabled and also not blocked by a higher priority interrupt. After the event is complete, software can manually return the device to
PMM. The following sources can trigger a switchback:
• External interrupt 0/1/2/3/4/5
• Serial start bit detected, serial port 0/1
• Transmit buffer loaded, serial port 0/1
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