DS89C420-QCL Datasheet, PDF (88/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
• Watchdog timer reset
• Power-on reset
• External reset
In the case of a serial port-initiated switchback, the switchback is not generated by the associated interrupt. This is because a device
operating in PMM is not able to correctly receive a byte of data to generate an interrupt. Instead, a switchback is generated by a ser-
ial port reception on the falling edge associated with the start bit, if the associated receiver enable bit (SCON0.4 or SCON1.4) is set.
For serial port transmissions, a switchback is generated when the serial port buffer (SBUF0;99h or SBUF1;C1h) is loaded. This ensures
the device is operating in divide-by-1 mode when the data is transmitted, and eliminates the need for a write to the CD1, CD0 bits to
exit PMM before transmitting. The switchback feature is unaffected by the state of the serial port interrupt flags (RI_0, TI_0, RI_1, TI_1).
The timing of the switchback is dependent on the source. Interrupt-initiated switchbacks occur at the start of the first clock cycle fol-
lowing the event initiating the switchback. In PMM, each internal clock cycle is 1024 external clock cycles. If the current instruction in
progress is a write to the IE, IP, EIE, or EIP registers, interrupt processing is delayed until the completion of the following instruction.
Serial transmit-initiated switchbacks occur at the start of the instruction following the MOV that loads SBUF0 or SBUF1. Serial recep-
tion-initiated switchbacks occur during the cycle in which the falling edge was detected. A few points must be considered when using
a serial port reception to generate a switchback. Under normal circumstances, noise on the line or an aborted transmission causes the
serial port to time out and the data to be ignored. This presents a problem if the switchback is used, however, because a switchback
would occur without indication to the system. If PMM and serial port switchback functions are used in a noisy environment, the user is
advised to periodically check if the device has accidentally exited PMM.
A similar problem can occur if multiprocessor communication protocols are used in conjunction with PMM. The ultra-high-speed flash
microcontroller family supports both the use of the SM2 flag (SCON0.5 or SCON1.5), and the slave address-recognition registers
(SADDR0;A9h, SADDR1;AAh, SADEN0;B9h, SADEN1;BAh) for multiprocessor communications. The problem is that an invalid address,
which should be ignored by a particular processor, still generates a switchback. As a result, it is not recommended to use a multi-
processor communication scheme in conjunction with PMM. If the system power considerations allow for an occasional erroneous
switchback, a polling scheme can be used to place the device back into PMM.
CLOCK SOURCE SELECTION
The ultra-high-speed flash microcontroller family supports three clock sources for operation. As with most microcontrollers, the device
can be clocked from an external crystal using the on-board crystal amplifier, or a clock source can be supplied by an external oscil-
lator. In addition, some members of the family incorporate an on-board ring oscillator to provide a quick resumption from stop mode.
The ring oscillator is a low power digital oscillator internal to the microcontroller. When enabled, it provides an approximately 10MHz
clock source for device operation without external components. The ring oscillator is not as stable as an external crystal, and software
should refrain from performing timing-dependent operations, including serial port activity, while operating from the ring oscillator.
The ring oscillator provides many advantages to the designers of microcontroller-based systems. One is that it allows Dallas
Semiconductor microcontrollers to perform a fast resume from stop mode, eliminating the crystal warmup delay when restarting the
device. The microcontroller must begin operation following a power-on reset from an external clock source, either an external crystal
or oscillator. The control and status bits which support the new and/or enhanced features are shown in Table 7-5.
Table 7-5. Clock Control and Status Bit Summary
BIT NAME
RGMD
LOCATION
EXIF.2
FUNCTION
Ring Oscillator Mode Status.
1 = Ring oscillator is current clock source,
0 = Crystal or external clock is current clock source.
RESET
0
WRITE ACCESS
None
RGSL
EXIF.1
Ring Oscillator Select, Stop Mode.
1 = Ring oscillator will be the clock source when
resuming from stop mode,
0 = Crystal or external clock will be the clock
source when resuming from stop mode
Note: Upon completion of crystal warm up period,
the device will switch to the crystal.
—
Unrestricted
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