DS89C420-QCL Datasheet, PDF (93/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
The watchdog interrupt usually has a different connotation than the timer interrupts. Unless the watchdog is being used as a very long
timer, the interrupt means that the software has failed to reset the timer and may be lost. The watchdog ISR can attempt to determine
the system state or allow the CPU to be reset if the watchdog reset function has been enabled (EWT = 1). Like other sources, the watch-
dog timer has a flag bit, enable bit, priority bits, and its own vector.
Serial Communication Interrupts
Each UART is capable of generating an interrupt. Each UART has its own interrupt enable, vector, and priority. Each UART interrupt
has two flags (RI, TI) that are used by the ISR to determine whether the interrupt comes from a received word or a transmitted one.
Unlike the timers, the UART flags are not altered when the interrupt is serviced. Software must change them manually.
When a UART finishes the transmission of a word, the TI bit is set and an interrupt is generated (if enabled). Likewise, the UART sets
the RI bit and generates an interrupt when a word is completely received. The CPU is not notified until the word is completely received
or transmitted.
Power-Fail Interrupt
The ultra-high-speed microcontroller has the ability to generate an interrupt when V_CC drops below a predetermined level. By com-
paring a fixed ratio of V_CC versus an internal reference, the microcontroller can assess when V_CC drops below the V_PFW level and
cause an interrupt (if enabled). The level of V_PFW is provided in the data sheet on DC electrical specifications. The power-fail interrupt
is a level-sensitive condition, and remains in effect as long as V_CC remains below V_PFW. The power-fail interrupt has the highest pri-
ority level, which cannot be altered by the user. The EPFI bit solely controls the enabling or disabling of the power-fail interrupt source,
and is not subject to the global interrupt enable (EA). The EPFI bit should always be cleared to a logic 0 state if the power-fail interrupt
is not needed.
Simulated Interrupts
Software can simulate any interrupt source by setting the corresponding flag bit. This forces an interrupt condition that is acknowledged
(if enabled) and is otherwise indistinguishable from the real thing. Thus, an interrupt flag bit should never be set to a logic 1 by soft-
ware inadvertently. Once an interrupt has been acknowledged, software cannot prevent or end the interrupt by clearing its flag. If, how-
ever, software clears an interrupt flag before the interrupt is acknowledged, the interrupt does occur.
INTERRUPT PRIORITIES
The ultra-high-speed microcontroller has five interrupt priority levels. The five priority levels, from highest priority to lowest, are 4, 3, 2,
1, and 0.
The power-fail interrupt, when enabled, always receives the highest priority (level 4), while the remaining interrupt sources can indi-
vidually be programmed to level 3, 2, 1, or 0. The lowest priority (level 0) is the default condition for the other sources. An interrupt
being serviced can only be interrupted by a higher priority interrupt. The power-fail interrupt source, assigned priority level 4, there-
fore, has the ability to interrupt the service routine of any other source. No interrupt source with equal or lesser priority to one current-
ly being serviced can interrupt the service routine.
If two interrupt sources of equal priority levels are requested simultaneously, natural priority is used to arbitrate. The natural priority is
given in Table 9-1. Note that natural priority is only used to resolve simultaneous requests. Once an interrupt of a given priority is
invoked, only a source that is programmed with a higher priority can intercede.
Interrupt Register Conflicts
During normal operation, there is a small but finite probability that application software might try to read or modify a register associat-
ed with interrupt functions at the same time that the interrupt hardware is modifying the register. In general, these hardware/software
interrupt conflicts are resolved according to the “hardware wins” philosophy: In the event of a conflict, the hardware modification of a
register takes precedence over the software action to ensure that the interrupt event is not missed.
To assist in prevention of hardware/software conflicts, the interrupt selection process that normally occurs in the final memory cycle of
each instruction is aborted for any instructions that write to the IP0, IP1, EIP0, EIP1, IE, or EIE registers. When the evaluation takes place
in the subsequent instruction, the interrupt source incorporates the new priority and enable values from the previous instruction. If this
situation occurs, it lengthens the interrupt latency by the length of the instruction that modified the register.
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